Design and Comparison of Multiplier using Vedic Sutras

Abstract

In this computational world, fast processing units are a requirement for many of real time applications. These units contain ALU and MAC as the fundamental blocks which are essential for efficient and fast execution. Multipliers are fundamentally utilized in Digital signal processors as its main component. To maintain the accuracy and increase the speed of execution multiplier, adder, registers have to be modified for which the ALU & MAC can have better performance. Design of faster multipliers is emphasized for its implementation in processors due to the increasing constraints on delay. To enhance the speed of multiplication, there is very high importance of designing faster multipliers. Among several multipliers, Vedic multipliers are preferred for their speed of operation, area usage and low power consumption over the other existing multipliers. Out of this, algorithms which are based on Vedic mathematics are intensive designing fast and low power multipliers. Vedic mathematics has sixteen sutras, out of which Urdhva Tiryakbhyam, Ekanyunena Purvena, Ekadhikena Purvena are discussed here along with simulation results. The focus of this paper is to achieve best results for area, speed, and power parameters for each of the sutras. Design of above four 16-bit sutras is carried out using Verilog language and is synthesized, simulated using Vivado 2017.1. Here, all the sutras are evaluated on basis of area, speed & power with existing research work.