Urdhva Tiryakbhyam Research Articles

IJARCCE - Computer and Communication Engineering

Reversible computation is an emerging area of research, having applications in nanotechnology, low power design and quantum computing. It is proved that reversible logic has zero internal power dissipation. Multiplication plays an important role in the processors. It is one of the basic arithmetic operations and it requires more hardware resources and processing time than the other arithmetic operations. Vedic mathematic is the ancient Indian system of mathematic. It has a unique technique of calculations based on 16 Sutras. The multiplication sutra between these 16 sutras is the Urdhva Tiryakbhyam sutra which means vertical and crosswise. In this paper it is used for designing a low latency and reduced resources 4*4 Vedic multiplier. The important parameters in designing reversible logic circuits like no of flipflops,no of LUT’s , Total Equivalent gate count for design are estimated and reported for our proposed reversible Vedic multiplier.

Ancient Vedic Multiplication Based Optimized High Speed Arithmetic Logic

Here, we deal with most effective Vedic multiplication method dependent 4*4 bit arithmetic logic unit having high speed. In this paper, we will perform ALU operations. ALU is a development of research work that has been done for years so we have chosen this topic. Normally ALU is a heart of digital processor, central processing unit, microprocessor and micro controller. Every digital domain based technology has to depend on the performance of ALU. Hence, there is a necessity of ALU which generates high speeds which depends on the speed of multiplier. Therefore, we go for designing a 4-bit multiplier. To generate high speeds, multiplier is employed which is one of the important blocks of the hardware unit and also an important initiation of delay in the path. We have studied many algorithms for multiplication technique but research says that Vedic multiplication is most effective of all in terms of speed. The algorithm contains 16 sutra, out of which we are employing URDHVA TIRYAKBHYAM and the code is written in Very High Speed Integrated Circuit Hardware Description. Our supporting synthesizing and simulating tools are Xilinx ISE9.2i and model sim-altra6.3g-pi (Quartus II) respectively. At last, we will compare 4-bit ALU with 4-bit Array ALU.

Design of Vedic Architecture for High Speed DCT

Discrete Cosine Transform (DCT) is a frequency transform which is extensively used as a transform codec for still, moving image and video compression. The performance of DCT architecture mainly depends on multiplier and adder. In conventional architecture, array multiplier and Ripple Carry Adder (RCA) gives enormous delay when the number of input bits become more. After having detailed literature review, it is decided to design high speed VLSI DCT architecture with Vedic Multiplier and Carry Select Adder (CSA) for better performance. The Vedic multiplier is based on Urdhva Tiryakbhyam, the most efficient Sutra or algorithm which reduces the delay for all types of computation. The functionality of the proposed architecture is simulated using Modelsim and synthesis of verilog HDL code is done using Xilinx ISE. Both the DCT architectures are compared and the result shows that the delay of Vedic multiplier becomes low. The synthesis results show that the combinational delay for Vedic multiplier is reduced by 36% than conventional array multiplier. The combinational delay for CSA is reduced by 35% than RCA. The proposed architecture would give better performance in terms of speed for image and other signal processing applications

Low Power High Speed 16x16 bit Multiplier using Vedic Mathematics

High-speed parallel multipliers are one of the keys in RISCs (Reduced Instruction Set Computers), DSPs (Digital Signal Processors), and graphics accelerators and so on. Array multiplier, Booth Multiplier and Wallace Tree multipliers are some of the standard approaches used in implementation of binary multiplier which are suitable for VLSI implementation. A simple digital multiplier (henceforth referred to as Vedic Multiplier in short VM) architecture based on the Urdhva Tiryakbhyam (Vertically and Cross wise) Sutra of Vedic Mathematics is presented. An improved technique for low power and high speed multiplier of two binary numbers (16 bit each) is developed. An algorithm is proposed and implemented on 16nm CMOS technology. The designed 16x16 bit multiplier dissipates a power of 0.17 mW. The propagation delay time of the proposed architecture is 27.15ns. These results are many improvements over power dissipations and delays reported in literature for Vedic and Booth Multiplier.

Delay-Power Performance Comparison of Multipliers in VLSI Circuit Design

A typical processor central processing unit devotes a considerable amount of processing time in performing arithmetic operations, particularly multiplication operations. Multiplication is one of the basic arithmetic operations and it requires substantially more hardware resources and processing time than addition and subtraction. In fact, 8.72% of all the instruction in typical processing units is multiplication. In this paper, comparative study of different multipliers is done for low power requirement and high speed. The paper gives information of “Urdhva Tiryakbhyam” algorithm of Ancient Indian Vedic Mathematics which is utilized for multiplication to improve the speed, area parameters of multipliers. Vedic Mathematics suggests one more formula for multiplication of large number i.e. “Nikhilam Sutra” which can increase the speed of multiplier by reducing the number of iterations.

High Speed Vedic Multiplier for Digital Signal Processors

Digital signal processors (DSPs) are very important in various engineering disciplines. Fast multiplication is very important in DSPs for convolution, Fourier transforms etc. A fast method for multiplication based on ancient Indian Vedic mathematics is proposed in this paper. Among the various methods of multiplications in Vedic mathematics, Urdhva tiryakbhyam is discussed in detail. Urdhva tiryakbhyam is a general multiplication formula applicable to all cases of multiplication. This algorithm is applied to digital arithmetic and multiplier architecture is formulated. This is a highly modular design in which smaller blocks can be used to build higher blocks. The coding is done in VHDL (very high speed integrated circuits hardware description language) and synthesis is done using Xilinx ISE series. The combinational delay obtained after synthesis is compared with the performance of the modified Booth Wallace multiplier which is a fast multiplier. This Vedic multiplier can bring about great improvement in DSP performance.