Abstract
In this research article, an improved area efficient 16-Quadrature Amplitude Modulation (QAM) transceiver design is introduced using Vedic multiplier. The 16-QAM design is transmitted using Pseudo Random Binary Sequence (PRBS) and modulated by changeable clock frequencies. The Vedic multiplier uses Urdhva Tiryakbhyam (Vertical and Crosswise) method of multiplication to reduce the undesirable steps and generates parallel partial products. Compressor adders are used in the Vedic multipliers, which helps to increase the speed of multiplication process and reduces the carry delay. Four Compressor adders namely 5-3, 10-4, 15-4 and 20-5 are used in a 16-bit Urdhva Tiryakbhyam Vedic multiplier to add its partial products. The proposed 16-QAM design is implemented using Spartan-3 XC3S200-5 pq208 Field Programmable Gate Array (FPGA) device which occupies 672 slices, 1102 4-input Look up Tables (LUTs) and 39 mW of power consumption. The Vedic multiplier based 16-QAM transceiver design reduces 17.2% slices and 4.5% 4-input LUTs. The 16-QAM is a preferred digital modulation method in the Orthogonal Frequency Division Multiplexing (OFDM) system, which reduces bit errors and noise effects during data transmission. The OFDM transceiver design is used in the high-speed wireless communication by excellence of its Multi-carrier modulation method.
Highlights
Today, the growth of wideband wireless communication system has been raised due to customer interest towards high-speed wireless communication in which Orthogonal Frequency Division Multiplexing (OFDM) transceiver design plays vital role
The different modulation techniques, such as Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), Offset Quadrature Phase Shift Keying (OQPSK), Quadrature Amplitude Modulation (QAM) etc., are used for Revised Manuscript Received on September 25, 2019
The Spartan 3 Field Programmable Gate Array (FPGA) device is fabricated on advance 90 nm technology can withstand up to 5 million system gates with the lowest cost and it is used for data communication applications
Summary
The growth of wideband wireless communication system has been raised due to customer interest towards high-speed wireless communication in which OFDM transceiver design plays vital role. There are various 16-QAM transceiver designs achieve an area efficient architecture in FPGA has been studied [4]–[7].The 16-QAM is a preferred digital modulation technique in wireless communication, which reduces noise effects and bit errors during data transmission. There is a requirement for implementing an area efficient QAM transceiver design. An improved area efficient 16-QAM transceiver design has been proposed. A 16-QAM transceiver design is selected for transmitting digital information towards band-pass channels to reduce bandwidth and increase the data rate. Urdhva Tiryakbhyam Vedic multiplier used in 16-QAM design provides an area efficient architecture. The Vedic multiplier based 16-QAM transceiver design implemented using Spartan 3FPGA, describes the step by step journey of signal transmission from source to destination with serial bit patterns.
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