An Area Efficient FFT Processor using Modified Compressor adder based Vedic Multiplier

Abstract

Fast Fourier Transform (FFT) technique has been used for processing the images, signals. It is used in spectrum analysis, sound filtering, image filtering, and data compression to name but a few. In the mentioned applications, FFT is used to translate the time domain signals into a spectrum representation. An optimized area for a 64-point FFT processor using a Vedic multiplier with a modified compressor adder has been proposed. Multi-radix approaches such as radix-23, radix-22, and radix-24 decrease the computational cost of the FFT processor. In the FFT processor, 8-bit Urdhva Tiryakbhyam vedic multipliers have been introduced, which reduces the total length of multiplication operations. A modified 4:2 Compressor adder will be used to speed up the vedic multipliers, minimizing carry delay. Urdhva Tiryakbhyam vedic multipliers uses modified compressor adders in the multi-radix FFT processor to reduce the silicon chip hardware area. The proposed multi-radix FFT processor uses a Field Programmable Gate Array (FPGA) chip named Virtex-6 XC6VLX75T device with 354S slice registers and 19247 slice Look up Tables (LUTs). It operates with a clock frequency of 148.57 MHz as its maximum. The FFT algorithm developed decreases the slice register to 87.8y% and slice LUTs to 48%. It operates by the clock frequency up to 148.57 MHz.