Performance evaluation of FFT processor using conventional and Vedic algorithm

Abstract

Recently digital signal processing has received high attention due to the advancement in multimedia and wireless communication. Accordingly Orthogonal Frequency Division Multiple Access (OFDM) technique based on Time Division Duplex (TDD) is an attractive technology for high data rate wireless access in multichannel communication. The modulation and demodulation of OFDM are done by Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) respectively. In this paper we propose a Vedic algorithm for the implementation of multiplier that is to be used in radix 25 512-point FFT processor. The multipliers based on Vedic mathematics are one of the fastest and low power multiplier. It enables parallel generation of partial product and eliminates unwanted multiplication steps. Thus Vedic multipliers ensure substantial reduction of propagation delay in FFT processor. The FFT processor employing Vedic multiplier reduces hardware complexity in area and power in FPGA implementation. The proposed processor has been designed in Xilinx and implemented using Spartan 3E FPGA kit with a supply voltage of 1.2 V. The delay and power obtained using the Vedic multiplier are 173.60ns and 11×10-2 W respectively.