High speed FFT processor design using radix −<sup>4</sup> pipelined architecture

Abstract

This paper present a design of Fast Fourier Transform (FFT) processor for high speed DSP application like OFDM based communication systems such as digital audio and video broadcasting (DAB & DVB), asymmetric digital subscriber loop (ADSL), where the basic need of this type of application is high speed processing on data. We designed high speed FFT processor with pipelined architecture which is efficient in terms of latency, with using fastest processing elements. In FFT processing, there are number of complex multiplication & addition operation. Multipliers takes more time for calculation therefore it increases the delay of FFT processor, hence the performance of processing element depends mostly on multipliers. We have designed the processing element i.e. floating point multiplier using two different types of fixed point multipliers, CSA multiplier which is conventionally high speed multiplier & Vedic multiplier based on Vedic mathematics. We have done the comparative analysis of CSA multiplier & Vedic multiplier on Xilinx 13.1i with Spartan-6 device (xc6slx100t-4-fgg900). Using these we have designed radix−4 pipelined architecture FFT processor.