Abstract

A practical fast Fourier transform (FFT) processor can contain several millions of gates, so effective design techniques usually are required in order to guarantee high-speed products. A look-up table (LUT) methodology is developed and demonstrated on variable length (128-1024 point), variable bit-precision (6-12 b) FFT with uniform bit truncation and optimum bit truncation for wideband digital receiver in radar applications. The FFT processors are designed using a standard 130 nanometer CMOS process and operates down to 120 mV. The required processing time for the non-configurable 12-b 1024-point LUT FFT is 15.78 ns at a clock frequency of 470 MHz. The required time for configurable LUT 12-b 1024-point FFT processing is 61 ns. The configurable LUT FFT processor with short transform lengths can be expandable so that they can be used easily to form new FFT processors with longer transform lengths. The performance comparison of conventional FFT, LUT FFT, and configurable LUT FFT for digital wideband receiver application is discussed.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.