Universal Verification Methodology Research Articles

A Review on Design and Verification of Programmable UART with AXI

A Review on Design and Verification of Programmable UART with AXI

Functional verification of QSPI module based on UVM implementation

This article presents a novel functional verification methodology based on the Universal Verification Methodology (UVM) to validate the functionality of the Quick Serial Peripheral Interface (QSPI) module. QSPI serves as a prevalent serial communication protocol widely employed for high-speed data exchange with external flash devices. By using the code coverage and functional coverage reports provided by UVM, we were able to assess how well the test cases covered the design code, identifying the parts of the design that had been adequately tested and those that needed more test coverage. This verification method based on UVM provides powerful tools and technical support for the design and development of the QSPI module and effectively ensures its reliability and stability. This study is of great significance for further improving the design quality and verification efficiency of the QSPI module.

A Universal-Verification-Methodology-Based Testbench for the Coverage-Driven Functional Verification of an Instruction Cache Controller

The Cache plays an important role in computer architecture by reducing the access time of the processor and improving its performance. The hardware design of the Cache is complex and it is challenging to verify its functions, so the traditional Verilog-based verification method is no longer applicable. This paper proposes a comprehensive and efficient verification testbench based on the SystemVerilog language and universal verification methodology (UVM) for an instruction Cache (I-Cache) controller. Corresponding testcases are designed for each feature of the I-Cache controller and automatically executed using a python script on an electronic design automation (EDA) tool. After simulating a large number of testcases, the statistics reveal that the module’s code coverage is 99.13%. Additionally, both the function coverage and the assertion coverage of the module reach 100%. Our results demonstrate that these coverage metrics meet the requirements and ensure the thoroughness of function verification. Furthermore, the established verification testbench exhibits excellent scalability and reusability, making it easily applicable to higher-level verification scenarios.

Hybrid Optimized Verification Methodology using Deep Reinforcement Neural Network

Universal Verification Methodology (UVM) caters to an essential role in verifying the different categories of circuits ranging from small-scale chips to complex system-on-chip architectures. Constrained random simulations are an indispensable part of UVM and are often used for design verification. However, the effort and time spent manually updating and analyzing the design input constraints result in high time complexity, which typically impacts the coverage goal and fault verification ratio. To overcome this problem, this paper proposes a novel hybrid optimized verification framework that combines Reinforcement Learning (RL) and Deep Neural Networks (DNN) for automatically optimizing the input constraints, accelerating faster verification with a high coverage ratio. The proposed algorithm uses reinforcement learning to generate all possible vector sequences needed for testing the target devices and corresponding outputs of the target devices and potential design errors. Furthermore, the framework intends to use high-speed deep-feedforward neural networks to automate and optimize the constraints during runtime. The proposed framework was developed using Python interfaced with the TCL environment. Extensive experimentation was carried out using several circuits, including multi-core designs, and performance parameters such as coverage accuracy, speed, and computational complexity were calculated and analyzed. The experiment demonstrated the proposed framework remarkable results, showing its superior performance in faster coverage and fewer misclassification errors. Furthermore, the proposed framework is compared with existing verification frameworks and other classical learning models. Good results demonstrate that the proposed framework increases the 4.5x speed for verifying multi-core designs and the 99% accuracy of detection and coverage.

A New FPGA-Based Task Scheduler for Real-Time Systems

This research demonstrates a novel design of an FPGA-implemented task scheduler for real-time systems that supports both aperiodic and periodic tasks. The periodic tasks are automatically restarted once their period has expired without any need for software intervention. The proposed scheduler utilizes the Earliest-Deadline First (EDF) algorithm and is optimized for multi-core CPUs, capable of executing up to four threads simultaneously. The scheduler also provides support for task suspension, resumption, and enabling inter-task synchronization. The design is based on priority queues, which play a crucial role in decision making and time management. Thanks to the hardware acceleration of the scheduler and the hardware implementation of priority queues, it operates in only two clock cycles, regardless of the number of tasks in the system. The results of the FPGA synthesis, performed on an Intel FPGA device (Cyclone V family), are presented in the paper. The proposed solution was validated through a simplified version of the Universal Verification Methodology (UVM) with millions of test instructions and random deadline and period values.

Universal verification methodology-based airborne electronic hardware certification approach for ARINC-429

PurposeThe purpose of this paper is to present a verification methodology for custom micro coded components designed for Avionics projects. Every electronic hardware which will be developed for an aircraft must be designed with the compliance of DO-254 processes. Requirements are the key elements of the aviation. All the requirements must be covered by the design to be considered as completed. Therefore, verification of the custom micro coded components against requirements should be comprehensively addressed. The verification using the manual testing approach is less preferable, as humans can possibly make mistakes. Therefore, the most used verification method today is the automated simulation.Design/methodology/approachThe industry has developed a common methodology for generating automated testbenches by following the standardized guideline. This methodology is named as the universal verification methodology (UVM). In this paper, the verification study of ARINC-429 data bus digital design is presented to describe the DO-254 verification process using the UVM.FindingsThe results are supported with functional coverage and code coverage in addition to the assertions. It is observed that the design worked correctly.Originality/valueTo the best of the authors’ knowledge, this is the first study comprehensively describing the DO-254 verification process and demonstrating it by the UVM application of ARINC-429 on programmable logic devices.

Design and verification of daisy chain serial peripheral interface using system Verilog and universal verification methodology

Serial peripheral interface (SPI) transfers the data between electronic devices like micro controllers and other peripherals. SPI consists of two control lines: select signal and clock signal, and two data lines: input and output. In single master-single slave, the communication is in between master and slave only which will make the design complex and costly, area will increase. In regular SPI mode, the number of chip-select lines is increased if the number of slaves increases. Due to this, the input data received by the master from the slaves are corrupted at master input slave output (MISO). The proposed daisy chain method is used to overcome this problem. The daisy chain method requires only one chip select line at master compared to the regular SPI mode. When the chip-select line is active low, all the slaves are active, and the clock is initiated to all the slaves to transfer the data from the master to the first slave through the master output slave input (MOSI). In this paper, the daisy-chain SPI is designed and developed using Verilog. The proposed design is verified using system Verilog (SV) and universal verification methodology (UVM) in QuestaSim.

Boosting chip verification efficiency: UVM-based adder verification with QuestaSim

The Very Large-Scale Integration (VLSI) industry is currently experiencing rapid growth in chip verification and design. This research focuses on generating a waveform, simulating, and verifying the Universal Verification Methodology (UVM) adder code using the QuestaSim tool and the UVM methodology. The functional verification community and researchers have an interest in UVM as it offers flexibility, reusability, and reliability properties that are useful for verifying complex chip systems. The main objective of this research is to verify the code of the UVM adder using the QuestaSim tool, which is a widely used tool for verifying digital circuits. Additionally, it aims to demonstrate the effectiveness of using the UVM methodology in verifying complex chip systems and highlights the importance of developing reliable and efficient verification methods for the VLSI industry.

Design and verification of memory by using UVM methodology

The design and verification of memory using the Universal Verification Methodology (UVM) methodology is discussed in this research. The advanced verification architecture uses a minimum number of macros, methods, and classes, and it provides high reusability for UVM tests. It makes use of the common attributes between different memory controllers to generate a common and configurable scoreboard, sequences, stimulus, different UVM components, and test cases. The memory controller provides a constructive control of data between the processor and memory. It provides modern structure and building blocks to work with codes, and it allows a dynamic approach. Simulation results show that the designed controller has a good performance and meets all the system specifications.

Study on Transformation to Universal Verification Methodology

Abstract: There are many approaches to the RTL design Verification. The different types of approach can be software simulation based, hardware accelerated simulation, formal verification etc. It helps to verify the correctness of the design, functional implementation and enhancing the design at every stage. Transition to Systemverilog has been done to cope up with the shrinking size of technology nodes and Time to market. In advanced times, the systems are to be designed in a generic way. The number of registers in the architecture increases as the number of combinations increases. Additionally, memory size is increasing as a result of the increased market need for data storage. An innovative approach is needed to access and validate the large variety of registers and the memory. A SystemVerilog class library called UVM was created specifically to support the creation of modular, reusable verification components and test-benches. Since it is an industry standard, you can use UVM IP that you obtain from other sources in your environment. You'll need to construct everything from scratch if you don't utilise UVM.

A Review on Design Implementation and Verification of AMBA AXI- 4 lite Protocol for SoC Integration

Abstract: The present modern bus protocols used for communication between different functional blocks on a System-on-Chip (Soc) designs face many different challenges among which complexity and communication management are the most important factors. These on-chip communications directly impact performance and functionality, hence depending on the application where the bus protocol is to be used, a perfect communication protocol is chosen. AMBA (Advanced Microcontroller Bus Architecture) provides various types of protocols to be used as IP, of which AXI4 (Advance Extensible Interface), is one of the widely used protocols for SoC designs. Out of its three different interconnect protocols: lite, stream and burst, AXI4-lite has the simplest architecture design that best suits to be used in applications where power, area and performance play a vital role. This paper briefs about using AMBA AXI4-lite bus protocol with more bus efficiency and performance in an SoC design for proper communication between various functional blocks present. The RTL is verified using UVM (Universal Verification Methodology) and various designing process is carried out using cadence tools.

A composite SystemC-UVM abstract optimal path selection verification architecture for complex designs

Universal Verification Methodology (UVM) architectures are highly trained for stimulus generation and verification of System-on-chip (SoC). The cross-functional and cross-platform interactive verification is the limitation of a sole UVM architecture. Sole UVM objects are not efficient to satisfy cross-functional compatibility requirements. A system C verification libraries have a mechanism of introspection. The data introspection is not capable of wide cross-platform use without reusable portable accurate TLM. So a UVM module requires a SystemC block to aim for the cross-functional working of verification. The work shows a composite UVM-SystemC methodology to rationally adhere to optimal test path selection among all test paths. The work presents SC-UVM (SystemC-UVM) architecture for cross-platform working facilitation. The learning methodology works to improvise coverage parameters with the optimization of coverage bins. The methodology earns a significant contribution for early verification by reducing the internal data processing and simulation time. The SystemC-UVM method outperforms the conventional SystemVerilog and Sole UVM verification techniques. The work declares the improvement of 5.26% in simulation time with 5.11% lesser data processing for database creation in front of the sole UVM verification architecture.

Verification methodology of a multi-mode radiation-hard high-speed transceiver ASIC

The second version of Low Power Giga Bit Transceiver (lpGBTv1) addresses the functional and radiation-related issues discovered during the testing of lpGBTv0 prototype. Considerable changes to the chip configuration architecture and flow were required. The Universal Verification Methodology (UVM) based verification environment was extensively refactored to address the functional verification challenges posed by the architectural changes in the chip. Additionally, the new UVM environment was designed to support extensive verification of robustness to Single Event Effects (SEE). In this paper we present the revamped UVM verification framework of lpGBTv1 and discuss the verification process, tools, techniques and metrics used to sign-off the design before submission.

A rigorous approach to microprocessor verification using UVM

In today's fast-paced technology industry, microprocessors play an increasingly important role in a wide range of applications. However, verifying the correctness of complex microprocessor designs remains a significant challenge. To address this issue, a rigorous approach to microprocessor verification using the Universal Verification Methodology (UVM) is proposed. UVM provides a standardised and scalable approach to verifying digital designs, including microprocessors, and has been widely adopted in the industry. This research proposes a UVM-based verification framework for microprocessors that can identify and eliminate design errors early in the development cycle. The proposed approach covers functional verification, performance verification, and hardware-software co-verification. The effectiveness of the proposed approach is evaluated through a case study of a commercial microprocessor design, where the UVM-based verification framework successfully detected and resolved several design bugs. The results demonstrate the potential of the proposed rigorous approach to microprocessor verification using UVM to enhance the quality and reliability of microprocessor designs.

Design and verification of an ARM Watchdog Timer using UVM

The watchdog timer is an advanced microcontroller bus architecture (AMBA) compliant system-on-chip peripheral. It is an AMBA slave module and connects to the advanced peripheral bus (APB). It consists of a 32-bit down counter with a programmable timeout interval that generates an interrupt and applies a reset to the processor on time out. Verification intellectual property (IP) is a smart way to verify the functional correctness of any complex design. This is achieved by constrained random verification (CRV), which generates legal test scenarios randomly that weed out the bugs and corner cases, thereby validating the characteristic features of the watchdog timer. CRV also builds automated checkers and provides higher coverage goals. In this work, an ARM Watchdog Timer is designed in Verilog and system-on-chip level verification of the same is performed using the universal verification methodology (UVM) by combining both CRV and coverage driven verification (CDV) to ensure its functional correctness.

Design And Verification Of Advanced Peripheral Bus Protocol Using Uvm

The System on chip uses advanced micro controller bus architecture is on chip bus introduced by ARM. Advanced peripheral bus is the component of the AMBA bus architecture. APB is low bandwidth, low power and low performance it used to connect the peripherals like UART, Keypad, Timer and other peripheral devices to the bus architecture. This introduces the AMBA APB bus using UVM architecture design. The design created using the Verilog and HDL and tested by Verilog test bench and design is verified using universal verification methodology. In this, we have a master and a slave. The master sends the control signals as a packet to the slave and the slave addresses the packet if both are equal we are getting transaction of write and read data, Where the master send the address slave recognize and it sends the signal to the master as a read data.

Verification of Wishbone Bus Interface for SoC using System Verilog and UVM

The Verification phase carries important role in design cycle of a system on chip. Verification gives with the actual enactment and functionality of a DUT and to verify the design meets the system requirements. This paper present wishbone bus interface for soc integration to interconnect architecture for portable IP cores and test bench is developed in system Verilog and verification is done by both system Verilog verification methodology and universal verification methodology which includes scoreboard, functional coverage and assertion. This paper based on two application to integrate IP cores that is single master with single slave interconnection and single master with multiple slave interconnections where master is test bench and slave will be a core.

Router1x3 Protocol Design Implementation and Verification with Virtual Cut through Mechanism for Network on Chip (NoC)

Hundreds of processors and memory cores are implemented on a single substrate called the System on Chip (SoC). The SoC with bus-based architecture has restrictions on the processing speed of the system and as the design becomes complex and the issue of scalability arises. Hence NoC is designed to enhance the scalability, data reliability, and processing speed with low power consumption by decoupling communication from computations [1]. Using NoC the IP cores of SoC are connected through on-chip routers and send data to each other through packet switching. The router is a processing chip that decides the right path for data transmission, hence the efficient design of the router is essential to enhance the performance and throughput of the system [2]. To reduces latency through the switch, the Virtual cut-through mechanism is a packet switching technique, in which the switch starts forwarding a packet as soon as the destination address is processed by header. Hence the present work focuses on a router input-output protocol design with the Virtual Cut-through mechanism for closed-loop communication. Router 1x3 has a single input port and three output ports. The architecture of Router 1x3 with sub-modules such as FIFO, FSM, Synchronizer, and Register is designed analyzed and verified using Verilog, System Verilog language, and Universal Verification Methodology(UVM). And it is also implemented on Xilinx 14.5 IDE with Spartan-6- XC6SLX45 FPGA.

Verification of Dual Port RAM using System Verilog and UVM

Verification process place a prominent role in the field of SoC and ASIC design. Several verification methodologies are there apart from those Universal Verification Methodology (UVM) is advanced and it is widely used by the industries due to its special features. UVM provides reusable and well-structured verification components by using System Verilog class library. In this work, Dual Port RAM is considered as Design Under Test (DUT). System Verilog and UVM verification environments are developed to verify the DUT. Assertion and cover group coverage are set up with a goal of achieving 100% from both the environments.

Verification of AMBA AHB Protocol using UVM

The project aims to verify the AMBA AHB protocol by using universal verification methodology is presented in this paper. Advanced high-performance(AHB) is used for communication of on chip bus which support single clock edge operation wider data 32/64/128 bit can be supported. The new verification constructs can be easily reused for the objected-oriented feature of universal verification methodology (UVM). Verification IP is the one which provides a smart way to verify the AHB Components. The advanced verification testbench incorporates the illustrations regarding simulation result are analysed to evaluate the effectiveness of the proposed testbench and functional coverage is to check functionality of the design. The self-checking mechanism using assertions improves the quality of UVM check by shortening time to debug and reducing time to cover for the in-depth understanding of test case output.