Verification methodology of a multi-mode radiation-hard high-speed transceiver ASIC

Abstract

The second version of Low Power Giga Bit Transceiver (lpGBTv1) addresses the functional and radiation-related issues discovered during the testing of lpGBTv0 prototype. Considerable changes to the chip configuration architecture and flow were required. The Universal Verification Methodology (UVM) based verification environment was extensively refactored to address the functional verification challenges posed by the architectural changes in the chip. Additionally, the new UVM environment was designed to support extensive verification of robustness to Single Event Effects (SEE). In this paper we present the revamped UVM verification framework of lpGBTv1 and discuss the verification process, tools, techniques and metrics used to sign-off the design before submission.