Functional verification of I2C core using SystemVerilog

Abstract

The verification phase carries an important role in design cycle of a System on Chip (SoC). A verification environment may be prepared using SystemVerilog without using any particular methodology but that will be different for every variation of the design. There are various verification methodologies out of which Universal Verification Methodology (UVM) is the state-ofthe-art and widely preferred by the verification industry worldwide, as the verification environment created using UVM is reusable, efficient and well structured. In this work we have compared the SystemVerilog and UVM verification environments. The Inter Integrated Circuit (I2C) Master Core is the Design Under Test (DUT). The environments created using SystemVerilog and UVM, completely wrap the DUT. The assertion coverage found is 100% from both approaches and functional coverage is found as 99.21% and 96.42% from SV environment and UVM environment respectively. Therefore, the overall coverage found is 99.60% and 98.21 from developed SV and UVM environment. Keywords : Environment, I2C, SoC, SystemVerilog, Testbench, Verification, UVM.