Abstract
Universal Verification Methodology (UVM) is a standardized hybrid methodology for verifying complex integrated circuit designs in the semiconductor industry. Predictor is a component in UVM based test bench that represents a golden model of the design under test (DUT), which generates an expected response against which the actual response of the DUT is compared in scoreboard. Predictors are mostly written in C or C++ for modelling the correct functionality of the DUT. It is provided in the form of compiled object code to the testbench and acts as a verification component. UVM uses SystemVerilog Direct Programming Interface (DPI) for communicating components written in C with other components of the test bench. This paper describes implementation of a UVM testbench consisting of a C based predictor, in the form of a complied object code for verification of a fused floating-point add-subtract design unit.
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