Study on Transformation to Universal Verification Methodology

Abstract

Abstract: There are many approaches to the RTL design Verification. The different types of approach can be software simulation based, hardware accelerated simulation, formal verification etc. It helps to verify the correctness of the design, functional implementation and enhancing the design at every stage. Transition to Systemverilog has been done to cope up with the shrinking size of technology nodes and Time to market. In advanced times, the systems are to be designed in a generic way. The number of registers in the architecture increases as the number of combinations increases. Additionally, memory size is increasing as a result of the increased market need for data storage. An innovative approach is needed to access and validate the large variety of registers and the memory. A SystemVerilog class library called UVM was created specifically to support the creation of modular, reusable verification components and test-benches. Since it is an industry standard, you can use UVM IP that you obtain from other sources in your environment. You'll need to construct everything from scratch if you don't utilise UVM.