Verification of Wishbone Bus Interface for SoC using System Verilog and UVM

Abstract

The Verification phase carries important role in design cycle of a system on chip. Verification gives with the actual enactment and functionality of a DUT and to verify the design meets the system requirements. This paper present wishbone bus interface for soc integration to interconnect architecture for portable IP cores and test bench is developed in system Verilog and verification is done by both system Verilog verification methodology and universal verification methodology which includes scoreboard, functional coverage and assertion. This paper based on two application to integrate IP cores that is single master with single slave interconnection and single master with multiple slave interconnections where master is test bench and slave will be a core.