Verification of Interconnection IP for Automobile Applications using System Verilog and UVM

Abstract

As the SoC complexity is increasing day by day to incorporate more functionalities, verification is also becoming complex and time consuming. To enable faster verification, a structured methodology is required. Universal Verification Methodology (UVM) is one such method consisting of a library of base classes based on SystemVerilog which can be extended for the required functionality. In this paper, an interconnection soft Intellectual Property (IP) used in automobile applications for incorporating complex functionalities is verified efficiently using UVM. The IP is highly programmable and parameterized for wide range of products. The basic metrics of verification, namely, code coverage and functional coverage are achieved in an efficient manner using the methodology. The code coverage was found to be 80.3% and functional coverage was found to be 82.08%.