AHB Protocol Verification Using Reusable UVM Framework and System Verilog

Abstract

Electronic circuits with reduced size can sustain high-performance operating at higher frequencies. This is possible due to System on Chip design. Multiple functional blocks are implemented in a single chip and the data transmission between multiple blocks might result in complications. Protocols are extensively used to connect IP blocks on Structured System On-Chips and are considered as the backbone for the SoCs. Advanced high-performance bus (AHB) protocol is a third-generation AMBA that is Advanced Microcontroller Bus Architecture specification designed by ARM which supports high-frequency data transmission. The AMBA AHB protocol standard is widely used for on-chip communication. This paper focuses on implementing working verification environments in System Verilog (SV) and in reusable Universal Verification Methodology (UVM) methodology to verify the AHB design specification along with their corresponding functional coverage to judge the quality of the environments. The read/write operations along with 16 beat wrapping and incrementing burst transfers are implemented and verified in verification environments. The functional coverage achieved in System Verilog is improved while working in UVM environment. There is a need for an efficient reusable framework to realize Coverage Driven Verification (CDC) which is provided by the universal verification methodology that results in a reduction of time expense to verify a design system from the very start. The simulation results for the implementations are obtained using QuestaSim 10.4e simulation tool.