Universal Gate Research Articles

Implementation of Geometric Quantum Gates on Microwave‐Driven Semiconductor Charge Qubits

AbstractA semiconductor‐based charge qubit, confined in double quantum dots, can be a platform to implement quantum computing. However, it suffers severely from charge noises. Here, a theoretical framework to implement universal geometric quantum gates in this system is provided. It is found that, while the detuning noise can be suppressed by operating near its corresponding sweet spot, the tunneling noise, on the other hand, is amplified and becomes the dominant source of error for single‐qubit gates, a fact previously insufficiently appreciated. It is demonstrated, through numerical simulation, that the geometric gates outperform the dynamical gates across a wide range of tunneling noise levels, making them particularly suitable to be implemented in conjunction with microwave driving. To obtain a nontrivial two‐qubit gate, a hybrid system is introduced with charge qubits coupled by a superconducting resonator. When each charge qubit is in resonance with the resonator, it is possible to construct an entangling geometric gate with fidelity higher than that of the dynamical gate for experimentally relevant noise levels. Therefore, the results suggest that geometric quantum gates are powerful tools to achieve high‐fidelity manipulation for the charge qubit.

All‐Resonance Controlled‐Phase Gate on Two Nonlocal Nitrogen‐Vacancy Center Ensembles Assisted by a Superconducting Quantum Circuit

AbstractThe realization of universal quantum logical gates on nonlocal nitrogen‐vacancy center ensembles (NVEs) is a basic task for universal quantum computing with NVEs. In contrast to previous works on the construction of gates, a one‐step all‐resonance scheme is proposed to construct a controlled‐phase gate on two nonlocal NVEs that are coupled to different superconducting transmission line resonators connected by a superconducting transmon qubit. The gate can be easily realized using only one step. Moreover, the all‐resonance operation allows the gate to be achieved within a short time. By considering the feasible parameters obtained in the experiments, this gate can be completed within 101 ns with a high fidelity of approximately 97.8%, which has reached the threshold of fault‐tolerance quantum computing.

The push-to-open mechanism of the tethered mechanosensitive ion channel NompC.

NompC is a mechanosensitive ion channel responsible for the sensation of touch and balance in Drosophila melanogaster. Based on a resolved cryo-EM structure, we performed all-atom molecular dynamics simulations and electrophysiological experiments to study the atomistic details of NompC gating. Our results showed that NompC could be opened by compression of the intracellular ankyrin repeat domain but not by a stretch, and a number of hydrogen bonds along the force convey pathway are important for the mechanosensitivity. Under intracellular compression, the bundled ankyrin repeat region acts like a spring with a spring constant of ~13 pN nm-1 by transferring forces at a rate of ~1.8 nm ps-1. The linker helix region acts as a bridge between the ankyrin repeats and the transient receptor potential (TRP) domain, which passes on the pushing force to the TRP domain to undergo a clockwise rotation, resulting in the opening of the channel. This could be the universal gating mechanism of similar tethered mechanosensitive TRP channels, which enable cells to feel compression and shrinkage.

Energy-efficient three-terminal SiO memristor crossbar array enabled by vertical Si/graphene heterojunction barristor

A three-terminal memristor is an electronic memory architecture that is particularly suitable for next-generation devices owing to its customizable intrinsic switching characteristics. However, its slow switching speed and lack of high-density array structure has hindered its applicability thus far. In this study, we have designed and fabricated a novel architecture by vertically integrating a silicon oxide (SiOx) memristor and a graphene barristor, which can be readily extended to a 16 × 16 crossbar array. Notably, the unipolar resistive switching of the SiOx memristor can be actively modulated by controlling a silicon (Si) phase filament via the barristor’s electrostatic gating. Such gate-tunable SiOx memristor in the array was observed to exhibit excellent electrical performance, e.g., increased switching speed (up to ~35 ns), increased switching probability, enhanced uniformity, and decreased operating voltage. The energy consumption is also significantly improved 4 nJ to 2 pJ via the gating, which exhibits lower than other three-terminal memristors. Moreover, it was able to sustain a high ON–OFF ratio (>106), multi-bit capability (~9 states), and stable endurance and retention properties regardless of gating. As an additional potential application, nonvolatile universal logic gates, including NOT, NOR, and NAND gates, were successfully implemented in this study based on simple circuits containing gate-tunable SiOx memristors. We believe that the proposed gate-tunable SiOx memristor represents a distinctive and novel development toward a fast, low energy, and extendable three-terminal memristor platform for electronic devices, thus undertaking a major step in unleashing the potential of memristors to support the growing demands of cutting-edge technologies.

FPGA Realization of Logic Gates using Neural Networks

The real time systems are designed by using analog and digital sub systems with control logic. In the design of digital sub systems the logic gates are the major building blocks. The Neural Networks found many applications in the areas of pattern recognition, prediction, artificial intelligence and other applications. Most of the Neural Network designs are realized by using software domain and hardware domains. This paper presents the hardware realization of logic gates using Neural Network. The logic gates like NAND, AND, NOR, OR, NOT, BUFFER are realized by using single layer neural network. The XNOR and XOR logic gates are realized by using structural representation of neural network based universal NAND gates. All the logic gates are realized by using Verilog HDL with Xilinx Vivado Design suite targeting for Xilinx Zynq-7000 SoC Evaluation Board. The Neural Network based logic gates are simulated for different test cases. Index Terms: Neural Network, Logic Gate, Zynq-7000 SoC, Verilog HDL, Xilinx Vivado EDA tool.

Bell-state tomography in a silicon many-electron artificial molecule

An error-corrected quantum processor will require millions of qubits, accentuating the advantage of nanoscale devices with small footprints, such as silicon quantum dots. However, as for every device with nanoscale dimensions, disorder at the atomic level is detrimental to quantum dot uniformity. Here we investigate two spin qubits confined in a silicon double quantum dot artificial molecule. Each quantum dot has a robust shell structure and, when operated at an occupancy of 5 or 13 electrons, has single spin-frac{1}{2} valence electron in its p- or d-orbital, respectively. These higher electron occupancies screen static electric fields arising from atomic-level disorder. The larger multielectron wavefunctions also enable significant overlap between neighbouring qubit electrons, while making space for an interstitial exchange-gate electrode. We implement a universal gate set using the magnetic field gradient of a micromagnet for electrically driven single qubit gates, and a gate-voltage-controlled inter-dot barrier to perform two-qubit gates by pulsed exchange coupling. We use this gate set to demonstrate a Bell state preparation between multielectron qubits with fidelity 90.3%, confirmed by two-qubit state tomography using spin parity measurements.

Fault-tolerant quantum data locking

Quantum data locking is a quantum communication primitive that allows the use of a short secret key to encrypt a much longer message. It guarantees information-theoretical security against an adversary with limited quantum memory. Here we present a quantum data locking protocol that employs pseudo-random circuits consisting of Clifford gates only, which are much easier to implement fault tolerantly than universal gates. We show that information can be encrypted into $n$-qubit code words using order $n - H_\mathrm{min}(\mathsf{X})$ secret bits, where $H_\mathrm{min}(\mathsf{X})$ is the min-entropy of the plain text, and a min-entropy smaller than $n$ accounts for information leakage to the adversary. As an application, we discuss an efficient method for encrypting the output of a quantum computer.

Realising and compressing quantum circuits with quantum reservoir computing

Quantum computers require precise control over parameters and careful engineering of the underlying physical system. In contrast, neural networks have evolved to tolerate imprecision and inhomogeneity. Here, using a reservoir computing architecture we show how a random network of quantum nodes can be used as a robust hardware for quantum computing. Our network architecture induces quantum operations by optimising only a single layer of quantum nodes, a key advantage over the traditional neural networks where many layers of neurons have to be optimised. We demonstrate how a single network can induce different quantum gates, including a universal gate set. Moreover, in the few-qubit regime, we show that sequences of multiple quantum gates in quantum circuits can be compressed with a single operation, potentially reducing the operation time and complexity. As the key resource is a random network of nodes, with no specific topology or structure, this architecture is a hardware friendly alternative paradigm for quantum computation.

Universal quantum control based on parametric modulation in superconducting circuits* *Project supported by the National Key Research and Development Program of China (Grant No. 2016YFA0301802), the National Natural Science Foundation of China (Grant Nos. 11474152, 12074179, and 61521001), and the Young Fund of Jiangsu Natural Science Foundation of China (Grant No. BK20180750).

As superconducting quantum circuits are scaling up rapidly towards the noisy intermediate-scale quantum (NISQ) era, the demand for electronic control equipment has increased significantly. To fully control a quantum chip of N qubits, the common method based on up-conversion technology costs at least 2 × N digital-to-analog converters (DACs) and N IQ mixers. The expenses and complicate mixer calibration have become a hinderance for intermediate-scale quantum control. Here we propose a universal control scheme for superconducting circuits, fully based on parametric modulation. To control N qubits on a chip, our scheme only requires N DACs and no IQ mixer, which significantly reduces the expenses. One key idea in the control scheme is to introduce a global pump signal for single-qubit gates. We theoretically explain how the universal gates are constructed using parametric modulation. The fidelity analysis shows that parametric single-qubit (two-qubit) gates in the proposed scheme can achieve low error rates of 10−4, with a gate time of about 60 ns (100 ns).

Quantum Logic Gates Based on DNAtronics, RNAtronics, and Proteintronics

Quantum computers (QCs) adopt an n‐state quantum mechanical system to manipulate the superposition state. However, molecular transistors are not used to build up the quantum logic gate. Herein, it is demonstrated that DNA, RNA, and protein are promising media for QCs, and one uses residue pairs, including nucleotide base pairs and amino acid pairs, via proton‐coupled electron transfer to fabricate a quantum logic gate. In the residue pair, the proton transfer between donor and acceptor states fulfills a qubit. Both the DNA‐CG (3‐qubit) nucleobase pair and nucleotide base pair obey the Toffoli gate. AT (2‐qubit) nucleotide base pair behaves as a SWAP gate and a CNOT gate. Furthermore, the AU and RNA‐CG nucleotide base pairs follow the CNOT gate and Toffoli gate, respectively. In addition, a pair of amino acids achieves 1‐qubit and satisfies the Pauli‐X, ‐Y, and ‐Z gates. The generators of universal quantum logic gates are obtained.

Noncyclic Geometric Quantum Gates with Smooth Paths via Invariant‐Based Shortcuts

AbstractNonadiabatic geometric quantum computation is dedicated to the realization of high‐fidelity and robust quantum gates, which are necessary for fault‐tolerant quantum computation. However, it is limited by cyclic and mutative evolution path, which usually requires longer gate‐time and abrupt pulse control, weakening the gate performance. Here, a scheme to realize geometric quantum gates with noncyclic and nonadiabatic evolution via invariant‐based shortcuts is proposed, where universal quantum gates can be induced in one step without path mutation and the gate time is also effectively shortened. Our numerical simulations show that, comparing with the conventional dynamical gates, the constructed geometric gates have stronger resistance not only to systematic errors, induced by both qubit‐frequency drift and the deviation of the amplitude of the driving fields, but also to environment‐induced decoherence effect. In addition, this scheme can also be implemented on a superconducting circuit platform, with the fidelities of single‐qubit and two‐qubit gates higher than 99.97% and 99.84%, respectively. Therefore, this scheme provides a promising way to realize high‐fidelity fault‐tolerant quantum gates for scalable quantum computation.

TVD‐PB logic circuit based on camouflaging circuit for IoT security

Internet of Things (IoT) devices are vulnerable to many physical attacks, including reverse engineering and side-channel analysis because the sensitive information of circuits may be leaked through the physical characteristics of the device. A logic camouflaging circuit is proposed that uses a balanced power consumption and threshold voltage-defined technique to provide an antiphysical attack scheme to protect the hardware security for IoT devices. The proposed circuit uses a symmetric differential pull-down network in implementing the different logic functions through the threshold voltage reconfiguration circuit. As a result, the power consumption of the circuit attains balance and stability between two different logical operations. The proposed threshold voltage-defined power-balance (TVD-PB) design is fabricated using a 65-nm CMOS technology, and the core area occupies approximately 0.0044 mm2, composed of NAND, NOR, XOR, and INV components and multiplier gates of the proposed TVD-PB circuit. The entire chip passed the logic function tests. The measured results show that the average similarity of the TVD-PB universal gate is 99.68%. In addition, the current margin is higher than 55 μA and power consumption of 0.455 mW during each clock cycle at 1.2 V derives 0.1072% of the normalized energy deviation and 0.0453% of the normalized standard deviation. Compared with other state-of-the-art techniques, the power dependency against power attacks is improved effectively.

Universal quantum gates, artificial neurons, and pattern recognition simulated by LC resonators

We propose to simulate quantum gates by \textit{LC} resonators, where the amplitude and the phase of the voltage describe the quantum state. By controlling capacitance or inductance of resonators, it is possible to control the phase of the voltage arbitrarily. A set of resonators acts as the phase-shift, the Hadamard and the CNOT gates. They constitute a set of universal quantum gates. We also discuss an application to an artificial neuron. As an example, we study a pattern recognition of numbers and alphabets by evaluating the similarity between an input and the reference pattern. We also study a colored pattern recognition by using a complex neural network.

Towards data-free gating of heterogeneous pre-trained neural networks

The combination and aggregation of knowledge from multiple neural networks can be commonly seen in the form of mixtures of experts. However, such combinations are usually done using networks trained on the same tasks, with little mention of the combination of heterogeneous pre-trained networks, especially in the data-free regime. This paper proposes multiple data-free methods for the combination of heterogeneous neural networks, ranging from the utilization of simple output logit statistics, to training specialized gating networks. The gating networks decide whether specific inputs belong to specific networks based on the nature of the expert activations generated. The experiments revealed that the gating networks, including the universal gating approach, constituted the most accurate approach, and therefore represent a pragmatic step towards applications with heterogeneous mixtures of experts in a data-free regime. The code for this project is hosted on github at https://github.com/cwkang1998/network-merging.

Bi2O2Se-Based Memristor-Aided Logic.

The implementation of two-dimensional materials into memristor architectures has recently been a new research focus by taking advantage of their atomic thickness, unique lattice, and physical and electronic properties. Among the van der Waals family, Bi2O2Se is an emerging ternary two-dimensional layered material with ambient stability, suitable band structure, and high conductivity that exhibits high potential for use in electronic applications. In this work, we propose and experimentally demonstrate a Bi2O2Se-based memristor-aided logic. By carefully tuning the electric field polarity of Bi2O2Se through a Pd contact, a reconfigurable NAND gate with zero static power consumption is realized. To provide more knowledge on NAND operation, a kinetic Monte Carlo simulation is carried out. Because the NAND gate is a universal logic gate, cascading additional NAND gates can exhibit versatile logic functions. Therefore, the proposed Bi2O2Se-based MAGIC can be a promising building block for developing next-generation in-memory logic computers with multiple functions.

Nonadiabatic geometric quantum gates that are insensitive to qubit-frequency drifts

Quantum manipulation based on geometric phases provides a promising way towards robust quantum gates. However, in the current implementation of nonadiabatic geometric phases, operational and/or random errors tend to destruct the conditions that induce geometric phases, thereby smearing their noise-resilient feature. In a recent experiment [Y. Xu et al., Phys. Rev. Lett. 124, 230503 (2020)], high-fidelity universal geometric quantum gates have been implemented in a superconducting circuit, which are robust to different types of errors under different configurations of the geometric evolution paths. Here, we apply the path-design strategy to explain in detail why both configurations can realize universal quantum gates in a single-loop way. Meanwhile, we purposefully induce our geometric manipulation by selecting the path configuration that is robust against the qubit-frequency-drift-induced error, which is the dominant error source on realistic superconducting circuits and has not been deliberately addressed. Moreover, our proposal can further integrate with the composite scheme to enhance the gate robustness, which is verified by numerical simulations. Therefore, our scheme provides a promising way towards practical realization of high-fidelity and robust nonadiabatic geometric quantum gates.

Discrete-time quantum walk on circular graph: Simulations and effect of gate depth and errors

We investigate the counterparts of random walks in universal quantum computing and their implementation using standard quantum circuits. Quantum walks have been recently well investigated for traversing graphs with certain oracles. We focus our study on traversing a 1D graph, namely a circle, and show how to implement a discrete-time quantum walk in quantum circuits built with universal CNOT and single qubit gates. We review elementary quantum gates and circuit decomposition techniques and propose a generalized version of all CNOT-based circuits of the quantum walk. We simulated these circuits on five different qubits IBM-Q quantum devices. This quantum computer has nonperfect gates based on superconducting qubits, and, therefore, we analyzed the impact of the CNOT errors and CNOT-depth on the fidelity of the circuit.

Cost-optimal single-qubit gate synthesis in the Clifford hierarchy

For universal quantum computation, a major challenge to overcome for practical implementation is the large amount of resources required for fault-tolerant quantum information processing. An important aspect is implementing arbitrary unitary operators built from logical gates within the quantum error correction code. A synthesis algorithm can be used to approximate any unitary gate up to arbitrary precision by assembling sequences of logical gates chosen from a small set of universal gates that are fault-tolerantly performable while encoded in a quantum error-correction code. However, current procedures do not yet support individual assignment of base gate costs and many do not support extended sets of universal base gates. We analysed cost-optimal sequences using an exhaustive search based on Dijkstra’s pathfinding algorithm for the canonical Clifford+Tset of base gates and compared them to when additionally includingZ-rotations from higher orders of the Clifford hierarchy. Two approaches of assigning base gate costs were used. First, costs were reduced toT-counts by recursively applying aZ-rotation catalyst circuit. Second, costs were assigned as the average numbers of raw (i.e. physical level) magic states required to directly distil and implement the gates fault-tolerantly. We found that the average sequence cost decreases by up to54±3%when using theZ-rotation catalyst circuit approach and by up to33±2%when using the magic state distillation approach. In addition, we investigated observed limitations of certain assignments of base gate costs by developing an analytic model to estimate the proportion of sets ofZ-rotation gates from higher orders of the Clifford hierarchy that are found within sequences approximating random target gates.

Efficient Decoding Scheme of Non-Uniform Concatenation Quantum Code with Deep Neural Network

How to design a universal fault-tolerant quantum computation protocol with high fidelity and low resource consumption is a hot topic in the field of quantum computing research. By reducing the effective code distance, the design of a universal fault-tolerant gate set based on concatenation code has been proposed. The auxiliary state required by the error correction of code must be verified before it can be used, so as to avoid the errors spread from the auxiliary state to the data state. But the qubit consumption can be very large due to multiple verification processes for the ancillary block. In this work, we analyze the ancillary consumption of two different verification schemes used in the Steane’s error correction process. We take the basic state preparation of a 25-qubit 2-level concatenation code as an example, adopt a simpler verification circuit in its error correction process, and design an efficient decoding strategy by using deep neural network algorithm. Numerical simulations are also performed to analyze our low qubit resource overhead error correction scheme.

Realization of arbitrary two-qubit quantum gates based on chiral Majorana fermions* *Project supported by the National Key R&D Program of China (Grant No. 2017YFA0303301), the National Natural Science Foundation of China (Grant No. 11921005), the Strategic Priority Research Program of Chinese Academy of Sciences (Grant No. XDB28000000), and Beijing Municipal Science & Technology Commission, China (Grant No. Z191100007219013).

Quantum computers are in hot-spot with the potential to handle more complex problems than classical computers can. Realizing the quantum computation requires the universal quantum gate set {T, H, CNOT} so as to perform any unitary transformation with arbitrary accuracy. Here we first briefly review the Majorana fermions and then propose the realization of arbitrary two-qubit quantum gates based on chiral Majorana fermions. Elementary cells consist of a quantum anomalous Hall insulator surrounded by a topological superconductor with electric gates and quantum-dot structures, which enable the braiding operation and the partial exchange operation. After defining a qubit by four chiral Majorana fermions, the single-qubit T and H quantum gates are realized via one partial exchange operation and three braiding operations, respectively. The entangled CNOT quantum gate is performed by braiding six chiral Majorana fermions. Besides, we design a powerful device with which arbitrary two-qubit quantum gates can be realized and take the quantum Fourier transform as an example to show that several quantum operations can be performed with this space-limited device. Thus, our proposal could inspire further utilization of mobile chiral Majorana edge states for faster quantum computation.