Unit Delay Model Research Articles

Path-Based Delay Variation Models for Parallel-Prefix Adders

State-of-the-art static timing analysis algorithms can evaluate worst-case delay in statistical terms. In this paper, a modeling framework is introduced for the evaluation of the maximum-delay Cumulative Density Function (CDF) of an ensemble of parallel-prefix adder topologies. For moderate variations and close-to-nominal supply voltages, the maximum delay of parallel-prefix adders is practically determined by the maximum of a set of near-critical-delay paths around the nominal maximum-delay path. These paths end to the most significant and neighboring bit positions. Matrix-based path delay formulations are derived for the particular set of paths. The introduced matrix formulations are exploited to assess the maximum-delay CDF by means of a multivariate Gaussian CDF. To validate the accuracy of the introduced models, a quantitative comparison of the proposed probabilistic delay models against Spice-level Monte-Carlo simulations is offered for certain parallel-prefix adders. Threshold-voltage variations summarize several process-dependent variation-inducing mechanisms and are modeled as Gaussian variations, introduced to BSIM-4 transistor models for a 16-nm technology node. For the nominal voltage case and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$10\%$</tex-math></inline-formula> threshold-voltage variations, the introduced models estimate the 0.95 timing yield point with a mean absolute error below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$1\%$</tex-math></inline-formula> compared to Spice-level simulations for the 16 bit-length case. Furthermore, an extension of the proposed approach to account for multiple end points is investigated that reduces the error for the estimation of maximum delay, demonstrated for a unit delay model and certain bit-lengths of Kogge-Stone adder.

Delay optimization for ternary fixed polarity Reed–Muller circuits based on multilevel adaptive quantum genetic algorithm

Delay optimization has now emerged as an important optimization goal in logic synthesis. The delay optimization for ternary fixed polarity Reed–Muller (FPRM) circuits aims to find a ternary FPRM circuit with a minimum delay. Because the delay optimization for ternary FPRM circuits is a combinatorial optimization problem, in this paper, we first propose a multilevel adaptive quantum genetic algorithm (MAQGA), which divides individuals into three-level populations: high-level population, intermediate-level population, and low-level population and uses the proposed ternary quantum rotation gate, proposed ternary quantum correction gate, and proposed multi-operator adaptive mutation mechanism to make the three-level populations evolve. Moreover, based on the proposed delay decomposition strategy, we propose a delay optimization approach (DOA) for ternary FPRM circuits under the unit delay model, which searches for a ternary FPRM circuit with a minimum delay using the MAQGA. Experimental results demonstrated the effectiveness and superiority of the DOA in optimizing the delay of ternary FPRM circuits.

EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model

Delay optimization has recently attracted significant attention. However, few studies have focused on the delay optimization of mixed-polarity Reed-Muller (MPRM) logic circuits. In this paper, we propose an efficient delay optimization approach (EDOA) for MPRM logic circuits under the unit delay model, which can derive an optimal MPRM logic circuit with minimum delay. First, the simplest MPRM expression with the fewest number of product terms is obtained using a novel Reed-Muller expression simplification approach (RMESA) considering don’t-care terms. Second, a minimum delay decomposition approach based on a Huffman tree construction algorithm is utilized on the simplest MPRM expression. Experimental results on MCNC benchmark circuits demonstrate that compared to the Berkeley SIS 1.2 and ABC, the EDOA can significantly reduce delay for most circuits. Furthermore, for a few circuits, while reducing delay, the EDOA incurs an area penalty.

Fuzzy delay model based fault simulator for crosstalk delay fault test generation in asynchronous sequential circuits

In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed. As design trends move towards nanometer technologies, more number of new parameters affects the delay of the component. Fuzzy delay models are ideal for modelling the uncertainty found in the design and manufacturing steps. The fault simulator based on fuzzy delay detects unstable states, oscillations and non-confluence of settling states in asynchronous sequential circuits. The fuzzy delay model based fault simulator is used to validate the test patterns produced by Elitist Non-dominated sorting Genetic Algorithm (ENGA) based test generator, for detecting crosstalk delay faults in asynchronous sequential circuits. The multi-objective genetic algorithm, ENGA targets two objectives of maximizing fault coverage and minimizing number of transitions. Experimental results are tabulated for SIS benchmark circuits for three gate delay models, namely unit delay model, rise/fall delay model and fuzzy delay model. Experimental results indicate that test validation using fuzzy delay model is more accurate than unit delay model and rise/fall delay model.

An efficient small‐delay faults simulator based on critical path tracing

SummaryTesting for small‐delay defects (SDDs) has become an important component of integrated circuit testing. In this paper, an efficient small‐delay fault simulator, a hybrid method combining forward serial simulation and backward critical path tracing simulation for SDDs is proposed, which aims to determine the coverage of small‐delay defects for a given test set fast and accurately. In our proposed method, a unit delay model is employed, and reconvergent sensitization as well as hazard‐based detection is considered. Signal waveforms are expressed by bitmap data forms. In addition to providing an accurate result for fault simulation, the proposed simulator can well assist test generation. Experimental results demonstrate that the proposed simulator can further accelerate the simulation by one or two orders of magnitude compared with previous works. Copyright © 2014 John Wiley &amp; Sons, Ltd.

Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.

On ATPG for Multiple Aggressor Crosstalk Faults

Crosstalk faults have emerged as a significant mechanism of circuit failure due to decreasing process geometries and increasing operation frequencies. Long signal nets are highly susceptible to crosstalk faults because they tend to have a higher coupling capacitance to overall capacitance ratio. Moreover, a typical long net also has multiple aggressors. In generating patterns to create maximal crosstalk induced delay on a victim net, it may be impossible to activate all aggressors logically or simultaneously to constructively induce maximum noise at the victim. Therefore, pattern generation must focus on activating a maximal subset of aggressors, weighted by actual coupling capacitance value, in close temporal proximity of the victim net transition. This max-satisfiability problem is constrained by fault effect propagation condition which involves determining an input signal assignment so as to propagate the fault effect at the victim to the primary output. In this paper, we present Automatic Test Pattern Generation (ATPG) solutions for multiple aggressor crosstalk faults for zero and unit delay models and compare the magnitude of crosstalk induced delay at the victim net. Our solution involves a combination of 0-1 Integer Linear Programming (ILP), for maximal aggressor excitation. Fault effect propagation is solved independently by using traditional stuck-at fault ATPG or by generating additional ILP constraints thus forming a integrated ILP formulation with error propagation. The effect of gate delays is summed by circuit transformation. The proposed technique was applied to ISCAS85 benchmark circuits. Results indicate that the percentage of total capacitance that can be switched varies from 75-100% for zero delay and 30-80% for variable delay case while achieving propagation of the fault effect to primary output.

Heuristics for Area Minimization in LUT-Based FPGA Technology Mapping

In this paper, an iterative technology-mapping tool called IMap is presented. It supports depth-oriented (area is a secondary objective), area-oriented (depth is a secondary objective), and duplication-free mapping modes. The edge-delay model (as opposed to the more commonly used unit-delay model) is used throughout. Two new heuristics are used to obtain area reductions over previously published methods. The first heuristic predicts the effects of various mapping decisions on the area of the final solution, and the second heuristic bounds the depth of the mapping solution at each node. In depth-oriented mode, when targeting five lookup tables (LUTs), IMap obtains depth optimal solutions that are 44.4%, 19.4%, and 5% smaller than those produced by FlowMap, CutMap, and DAOMap, respectively. Targeting the same LUT size in area-oriented mode, IMap obtains solutions that are 17.5% and 9.4% smaller than those produced by duplication-free mapping and ZMap, respectively. IMap is also shown to be highly efficient. Runtime improvements of between 2.3times and 82times are obtained over existing algorithms when targeting five LUTs. Area and runtime results comparing IMap to the other mappers when targeting four and six LUTs are also presented

Optimal clock period clustering for sequential circuits with retiming

In this paper we consider the problem of clustering sequential circuits subject to a bound on the area of each cluster, with the objective of minimizing the clock period. Current algorithms address combinational circuits only, and treat a sequential circuit as a special case, by removing all flip-flops (FF's) and clustering the combinational part of the sequential circuit. This approach breaks the signal dependencies and assumes the positions of FF's are fixed. The positions of the FF's in a sequential circuit are in fact dynamic, because of retiming. As a result, current algorithms can only consider a small portion of the whole solution space. In this paper, we present a clustering algorithm that does not segment circuits by removing FF's. In additional, it considers the effect of retiming. The algorithm can produce clustering solutions with the optimal clock period under the unit delay model. For the general delay model, it can produce clustering solutions with a clock period provably close to optimal.

On nominal delay minimization in LUT-based FPGA technology mapping

In this paper, we study the LUT-based FPGA technology mapping problem for delay minimization under the nominal delay model, which assumes that the interconnect delay of a net is proportional to the fanout size of the net. First, we show several complexity results on LUT mapping under the nominal delay model. We prove that the delay-optimal K- LUT mapping problem under the nominal delay model is NP-hard when K ≥ 3, and remains NP-hard for duplication-free mapping and tree-based mapping when K ≥ 5. Then, we show that for K = 2 the delay-optimal duplication-free mapping problem or tree-based mapping problem under the nominal delay model can be solved in polynomial time. Finally, we develop a heuristic LUT mapping algorithm for nominal delay minimization on general K- bounded Boolean networks. Experimental results have shown that our heuristic algorithm can produce mapping solutions of smaller delay compared with the solutions of the depth-optimal mapping algorithm under the unit delay model.

LUT-based FPGA technology mapping under arbitrary net-delay models

The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. Most existing algorithms for performance-driven technology mapping for Lookup-table (LUT)-based FPGA designs are based on the unit-delay model. In this paper we study the technology mapping problem under arbitrary net-delay models. We show that if the net delay can be determined or estimated before mapping, the problem can be optimally solved in polynomial time based on efficient network flow computation. We have implemented the algorithm and tested it on a number of MCNC benchmark examples.

Efficient timing verification via mixed-mode technique

A new mixed-mode timing verifier for CMOS circuits is presented. It enables a designer to uncover the slowest signal paths in a circuit, which is modelled by logic gates, transistors and interconnections. First, to find all signal paths, the path generation is performed. It proceeds with unit-delay models and a depth-first search. Next, the breadth-first delay analysis takes place, which is based on accurate gate and switch-level multiple-delay models. While gate delays are evaluated by table lookup, for tightly coupled transistor stages with parasitic interconnection elements more sophisticated method is exploited. Stages with a quickly changing input signal are analysed by means of a semianalytic approach, based on a single transistor trigger. For slowly changing input, however, to be adequate to the gate delay estimates and to keep the accuracy, a pair of complementary transistor triggers (i.e. the N-pulldown and the P-pullup) is used. In this case a relaxation-based timing analysis is performed. The experimental results of this method are compared to SPICE's estimates. While the maximum errors for individual paths are shown to lie within 10%, the average ones are typically within 5%.

An optimistic ternary simulation of gate races

The detection of timing problems in digital networks is of considerable importance. In particular it is desirable to have efficient methods for discovering critical races and hazards. Unfortunately, commercial simulators rarely provide such facilities; in fact, the simulators usually assume that all the gate delays are exactly equal. In contrast to this, binary race analysis frequently assumes that gate delays can be arbitrarily large, though finite. An exception to this is the almost-equal-delay race model, where gates have different delays, but the difference between any two delays cannot be arbitrary. The difficulty with the use of this model is that it is computationally very inefficient. In this paper we define a new ternary model which is very closely related to the binary almost-equal-delay model. Moreover, the ternary model is considerably more efficient, as efficient as the unit delay model; consequently, it could easily be incorporated in simulators.

Estimation of coefficients for multiple input system models without employing common denominator structure

An instrumental variable (IV) parameter estimation scheme is presented for transfer function coefficient estimation. It is applied to some elementary multiple-input single-output (MISO) linear system models. The discrete unit delay (z-transform) model form is employed with both similar and dissimilar denominator polynomials. The efficacy of the proposed scheme is illustrated by means of results obtained in single stochastic simulation experiments. Although more convergence difficulties are encountered with the dissimilar denominator model structure, the is in a more general form because the independent auto-regressive (All) components within the assumed noise disturbance dynamics are immediately available. The dissimilar denominator MISO model structure is formulated as superimposed single-input single-output (SISO) models. Convergence difficulties are mainly experienced because of the need to estimate the individual output series associated with each of the SISO models. The present results suggest that t...