Efficient timing verification via mixed-mode technique

Abstract

A new mixed-mode timing verifier for CMOS circuits is presented. It enables a designer to uncover the slowest signal paths in a circuit, which is modelled by logic gates, transistors and interconnections. First, to find all signal paths, the path generation is performed. It proceeds with unit-delay models and a depth-first search. Next, the breadth-first delay analysis takes place, which is based on accurate gate and switch-level multiple-delay models. While gate delays are evaluated by table lookup, for tightly coupled transistor stages with parasitic interconnection elements more sophisticated method is exploited. Stages with a quickly changing input signal are analysed by means of a semianalytic approach, based on a single transistor trigger. For slowly changing input, however, to be adequate to the gate delay estimates and to keep the accuracy, a pair of complementary transistor triggers (i.e. the N-pulldown and the P-pullup) is used. In this case a relaxation-based timing analysis is performed. The experimental results of this method are compared to SPICE's estimates. While the maximum errors for individual paths are shown to lie within 10%, the average ones are typically within 5%.