Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits

Omnia S Ahmed,Mohamed F Abu-Elyazeed,Hassanein H Amer,Mohamed B Abdelhalim,Ahmed H Madian

doi:10.4236/cs.2013.43037

Abstract

In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes’ toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlosimulation methods.

Highlights

A fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed
The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlo simulation methods
Power dissipation is an important parameter for digital VLSI circuits as the excessive power consumption may lead to runtime errors or permanent damages due to overheating

Summary

Introduction

Power dissipation is an important parameter for digital VLSI circuits as the excessive power consumption may lead to runtime errors or permanent damages due to overheating. For simulative-based methods, the circuit is simulated with different inputs to obtain the power consumption. The main problems in simulative-based methods are the large memory requirements, time consumption and how to find the representative input vector set needed to exercise the circuit. In [10], an accurate method was introduced for calculating the average and the maximum dynamic power at the gate level. The logic picture concept was modified in [11] to calculate the average power consumption for sequential circuits. The proposed method is backward-compatible as it can be modified to obtain the power consumption for the zero-delay gate model.

Methodology

Experimental Results

Conclusion