Power-delay Trade-offs in CMOS Circuits Using Self-bias Transistors

Abstract

Power dissipation and propagation delay are contradicting factors in the design of VLSI CMOS circuits. This paper investigates CMOS circuits with Self-Bias Transistors (SBTs) connected between the pull-up/down network and the supply rails. Previous research on circuits with SBTs shows substantial reduction in leakage power of combinational circuits. We extend the analyses by studying both static and dynamic power and also propagation delay for combinational as well as sequential circuits. Transistor-level dual-Vt technique is employed for combinational circuits with SBTs to achieve a good power and delay trade-off by selecting different transistors in the circuit to have different Vt. Extensive HSPICE simulations were performed with 0.18 μm CMOS technology. Results show that on average, a 45% reduction in static power and 17% reduction in dynamic power can be achieved by employing SBTs in combinational CMOS circuits. Similar results for sequential CMOS circuits are also included. Simulation results for propagation delay and power-delay trade-off are also presented.