Uniform Doping Profile Research Articles

The Effect of Collector Region Design on Large-Signal Performance of Horizontal Current Bipolar Transistor (HCBT)

The impact of collector region design on large-signal performance of horizontal current bipolar transistor (HCBT) technology is investigated by calibrated time-domain load-pull measurements. Three representative high-performance devices of the same geometry but with different collector doping profiles, namely, uniform, n-well, and low-doped, are subjected to large-signal measurements wherein the radio frequency (RF) time-domain waveforms of current and voltage are measured to facilitate the determination of the maximum output power for each device. The extensive measurements outline the boundaries of the maximum collector current and voltage swings at RF determining linear operating area, which are a result of the physical phenomena in the high-current and high-voltage regimes, namely, the Kirk effect and impact ionization, respectively. While the highest-doped n-well HCBT provides the highest output power of 25.3 dBm at 1-dB gain compression, and the lowest-doped HCBT enables a wideband match at the collector, the HCBT with a uniform doping profile provides a tradeoff between the output power and bandwidth of the output match. The results show the versatility of HCBT technology as an alternative to CMOS and/or sillicon–germanium (SiGe) large-signal RF circuits for the front-ends (FEs) in the sub-6 GHz wireless communications range.

A uniform ion doping air-hole-assisted FM-EDF for low differential modal gain

An air-hole-assisted few-mode erbium-doped fiber (AH-FM-EDF) with a uniform erbium ion doping profile is proposed for gain equalization. By introducing the central air hole, the mode field distribution is strongly modified, contributing to a significant improvement in reducing the differential modal gain (DMG). Numerical results show that the gains of each mode can all reach 20 dB and the DMG is about 0.4 dB at 1550 nm in either core-pumping or cladding-pumping cases. Besides, the amplifier is well-behaved in gain-flattening with a noise figure (NF) of about 4.5 dB over the whole C-band. The proposed fiber shows much flexibility and robustness in gain equalization due to its simple uniform doping profile and pump-mode selection.

β -Ga2O3 MESFETs with insulating Mg-doped buffer grown by plasma-assisted molecular beam epitaxy

In this work, we develop in situ Mg doping techniques in plasma-assisted molecular beam epitaxy (PAMBE) of β-Ga2O3 to compensate Si dopants at the substrate epilayer growth interface and eliminate parasitic leakage paths. Both abrupt and uniform Mg doping profiles over a wide range of concentrations were achieved in β-Ga2O3 epilayers grown by PAMBE. Capacitance–voltage characteristics of Si and Mg co-doped samples confirmed the compensating effect of the Mg dopants. Mg delta-doping was then integrated into a β-Ga2O3 metal-semiconductor field effect transistor structure and shown to be effective in eliminating source leakage. The results presented here show that Mg doping is a promising way to engineer insulating buffer layers for β-Ga2O3 lateral devices grown by PAMBE.

Investigation of NBTI Effect in P-Type Junctionless Transistor with Uniform and Graded Doping Profiles

This paper presents the reliability effect analysis of Negative Bias Temperature Instability (NBTI) in p-type junctionless transistor (JLT) under uniform and non-uniform doping profiles using Global TCAD Solution. The work compares the change in threshold voltage ( $$\Delta {Vth}$$ ) with the stress time and relaxation time for uniform and non-uniform doping profile in long and short channel p-type JLT. When negative Vgs and Vds are applied in the device, large number of interface traps are generated due to the dissociation of Si–H bonds along with the silicon-oxide interface. This results in the subsequent increase in the threshold voltage (Vth), thereby decreasing the driving capability and hence affects the device performance. Further, it is observed, increase in temperature causes more increase in the threshold voltage (Vth). This effect is due to breaking of more Si–H bonds, generating more interface traps. Simulation results after comparison shows that this change in $$\Delta {Vth}$$ under stress is more in non-uniform than in uniform p-type JLT, this is due to the fact that an increase of trap charges on uniform p-type JLT is less compared to non-uniform p-type JLT. It is also observed that short-channel devices are more prone to NBTI effect.

Thin film solar cell efficiency enhancement using a gradient doping absorbent layer

In this contribution, we propose a numeric exploration of a copper indium gallium diselenide (CIGS) based thin film solar cell structure by means of SILVACO's technology computer aided design (T-CAD). We found the performance of our proposed cell and that of experimental champion very similar. High resistance and surface recombination near the rear contact alongside with bulk recombination reduce solar cell performance. In order to get a cell performance enhancement, we suggest the introduction of an additional electric field via gradient doping in absorbent layer in order to reduce the latter phenomenon effects. Therefore, both graded and uniform doping profiles have been studied then compared. Our results demonstrated that the graded doping in CIGS absorbent layer gives higher conversion efficiency (η) than uniform one. Structure with 0.11, 0.04, 0.01, and 2 μm thicknesses of MgF2, n-ZnO, n-CdS, and p-CIGS layers, respectively, gives the best performance. A graded doping of (3 × 1016-1022) cm−3 concentration in CIGS layer, 1022 cm−3 in ZnO layer, and 1021 cm−3 in CdS layer give a conversion efficiency of 29.43% in comparison to 22.92% of the proposed cell at room temperature.

Influence of the Biomaterial Thickness in a Dielectrically Charged Modulated Fringing Field Bio-Tunnel-FET Device

The biosensor market is expected to increase more than 40% in 5 years ( 2019 to 2024) due to the versatile of these devices (1). Many research groups are studying new types and optimizations of these devices and the tunnel field-effect transistors (TFET) have attracted the interest due to the many advantages of these devices (2).Figure 1 shows the Bio-TFET cross section which has been simulated with TCAD Sentaurus (3). The proposed device has a gate length (LG), equivalent gate oxide thickness (tox) and channel silicon thickness (tSi) of 40 nm, 1 nm and 10 nm. The drain underlap (LUD) is variable in the range of 1 to 100 nm. The uniform doping profile of the device consists of a source and drain doping concentration of 1020 atom/cm3 of boron and arsenic, respectively. An intrinsic channel with 1015 atom/cm3 of boron. The gate electrode has a workfunction of 4.7 eV. The main models incorporated in the simulation were the bandgap narrowing (BGN), Shockley Read Hall recombination (SRH) and the nonlocal band-to-band tunneling (BTBT). In the drain underlap region is deposited a biomaterial for biosensing purposes. This material has a dielectric constant (k, where ε=k*ε0) of 1 (air), 2.1 (Streptavidin), 3.57 (APTES), 8 (Anti-Iris antibody) and 10 (Isoquinoline) (4).Figure 2 shows the Bio-TFET transfer characteristics. The ambipolar region is a parasitic tunneling current that occurs for negative gate bias (VG) for nTFET at drain to channel region. In order to decrease this effect a drain underlap (LUD) is performed at the device (5). However, when the biomaterial dielectric constant (k) increases, the ambipolar current also increases orders of magnitude, meaning that the device is very susceptible to k variation in the biomaterial region and can be used for biosensing of different types of biomolecules with a distinct k. In order to quantify the influence of change in k in the biomaterial region the equation in terms of ID: Sensitivity = ΔID/ID(Ref.) was used. Where ΔID represents the difference between the drain current of biosensing (output), e.g., the drain current with the presence of biomaterial ID(Bio) and the drain current of reference ID (Ref.) (input), e.g., drain current without biomaterial ID (k=1) . Both for a fixed value of gate voltage (VG = -2 V) in the ambipolar region. Fig.3 shows the sensitivity of the device as a function of LUD for different k values. The maximum sensitivity occurs for a LUD = 30 nm for all range of k values. The sensitivity increases for higher k as reported in (6). Another parameter that is important for sensing is the dimension of the target. Many biomolecules have different types, e.g., spherical, ellipsoidal or elongated (7). Therefore, the study of the parameter is fundamental for the functional operation of the device. In Fig.4 the sensitivity is analyzed as a function of biomaterial thickness (tBio) for a fixed value of LUD=30nm. With the rising of tBio and k the sensitivity increases, i.e., exceeding 2 orders of magnitude comparing tBio = 10nm and tBio = 30 nm for k = 10. This increment on sensitivity is due to the tunneling length lowering, as can be noticed in Fig.5. The tunneling length decrease from 5.7 nm (tBio= 10 nm) to 9.5 nm (tBio = 30 nm), both for k = 10 and fixed energy of - 1 eV. The lowering of the tunneling length increases the ambipolar current ID(Bio) that enhances the sensitivity of the device. An important consideration for the biosensing process is the charge on the biomaterial that affect the tunneling current and therefore affect the sensitivity of the device. In Fig. 6, the sensitivity is studied as in the function of positive fixed charges in the range of 1010 to 1012 cm-2. The sensitivity increases for thicker values of tBio. This is due to the higher effect of the fringing field in the region. As tBio increase the effect of fringing field increases in the biomaterial region and as consequence, the device becomes more sensible with the presence of charges.The study of charges and biomaterial thickness in a dielectrically modulated fringing field Bio-TFET was performed in this work. The device shows high sensitivity with the increase of tBio in the range studied in this work. Although, the effect of fixed charges is more notable for thicker tBio. Then, the tBio thickness shows a high impact in the sensing of the device. Figure 1

Horizontal Current Bipolar Transistor (HCBT) Technology for High Linearity RF Mixers

The high linearity downconversion active mixers are demonstrated in the horizontal current bipolar transistor (HCBT) technology. The HCBTs fabricated by uniform n-collector doping profile, long hydrofluoric (HF) etching, and long tetramethylammonium hydroxide (TMAH) etching are shown to be optimal for mixer performance. The circuits fabricated with the optimum HCBTs in 180-nm bipolar complementary metal-oxide semiconductor (BiCMOS) process are packaged and measured, resulting in the best HCBT mixer characteristics published so far. The HCBT mixer uses a double-balanced Gilbert cell core with an integrated local oscillator (LO) buffer driver and employs an open-collector output topology. It provides broadband operation and frequency downconversion, measured up to 3 GHz, with a maximum power consumption of 550 mW at the peak linearity performance. The measured peak input third-order intercept point (IIP3) and conversion gain (CG) of 30.3 dBm and 6.0 dB, respectively (at 900-MHz input), are suitable for the base station transceivers and wireless infrastructure. The HCBT technology represents a low-cost BiCMOS platform capable of meeting the various requirements in the fabrication of the radio frequency integrated circuits (RFICs).

Electrically Active Defects in Plated Crystalline Silicon n+p Solar Cells: A DLTS Perspective

Cost reduction is one of the major driving forces in the technology development of silicon solar cells. This explains the current interest in the implementation of a copper-based metallization, replacing more expensive Ag contacts [1-3]. In order to prevent the in-diffusion of copper in the underlying silicon substrate, a diffusion barrier, like, e.g., a thin nickel layer is usually deposited. Opening of the passivation layer for contact formation by laser ablation (LA), enables a better controll for narrower line features, compared with standard wet etching. In this work, potential issues with defect fomation associated with laser ablation and metal plating will be studied relying on Deep-Level Transient Spectroscopy (DLTS) [4]. P-doped emitters have been fabricated by POCl3 diffusion into 1-3 Wcm p-type Czochralski silicon substrates. Passivation of the solar cells has been achieved by PECVD of a SiNx:H layer. The dielectric layer at the front was opened by ps UV-laser ablation, using a high fluence (1.08 J/cm2) (hard LA). This was compared with wet etching (WE). Approximately 1 mm of nickel was deposited by light-induced plating, followed by 8 to 10 mm of electroplated copper. More details of the processing have been previously reported [5,6]. Diodes with area of 2 mmx2 mm were laser-cut from the finished solar cells for DLTS, using a Fourier-Transform (FT) system. Temperature (T-) scans have been performed at different bias pulses from a reverse bias VR to a pulse bias VP, for different durations tp. The pulse period was tw. Before cooling the sample, Current-Voltage (I-V) and Capacitance-Voltage (C-V) measurements have been performed at room temperature, the latter at a fixed frequency of 1 MHz. Normal I-V and C-Vs have been obtained (Fig. 1), while rather uniform doping profiles were derived from a 1/C2 versus VR plot (Fig. 2), yielding a doping density in the range of 2×1016 cm-3. The spectra for the wet etched sample in Fig. 3 exhibit two main hole traps in the p-type base layer: a peak at about 80 K and another one at ~150 K. The activation energy of the first trap amounts to 0.17 eV and a hole capture cross section sp of ~7×10-15 cm2. Applying a minority carrier injection pulse to forward VP, reveals a clear electron trap at about the same position in Fig. 4, followed by a second one at higher T. It has been shown elsewhere that the 0.17 eV peak most likely corresponds with the substitutional nickel donor level [5]. The shallow electron trap could well be the double acceptor level of Nis at EC-0.07 eV, while the deeper one may correspond with the first acceptor level. The LA sample exhibits the same 80 K hole trap as after wet etching (Fig. 5), indicating that the nickel-silicidation process introduces nickel in the underlying p-type base, irrespective of the etching. A deeper hole trap at about 200 K is observed as well and could be related to dislocation-related states [5,6]. Further proof of that is the observation of slow capture by the nickel donor level in Fig. 6, which follows an ln(tp) dependence. The capture is much slower than can be expected from the hole capture cross section and indicates that Nis may be trapped in the strain field around the dislocations, penetrating the p-type base. Similar observations have been found in the past for Fe decorating dislocations in p-type silicon [8]. It will, finally, be shown that in both cases, no active copper levels have been detected in the p-type silicon base [5,6].

Nanowire Kinking Modulates Doping Profiles by Reshaping the Liquid-Solid Growth Interface.

Dopants modify the electronic properties of semiconductors, including their susceptibility to etching. In semiconductor nanowires doped during growth by the vapor-liquid-solid (VLS) process, it has been shown that nanofaceting of the liquid-solid growth interface influences strongly the radial distribution of dopants. Hence, the combination of facet-dependent doping and dopant selective etching provides a means to tune simultaneously the electronic properties and morphologies of nanowires. Using atom-probe tomography, we investigated the boron dopant distribution in Au catalyzed VLS grown silicon nanowires, which regularly kink between equivalent ⟨112⟩ directions. Segments alternate between radially uniform and nonuniform doping profiles, which we attribute to switching between a concave and convex faceted liquid-solid interface. Dopant selective etching was used to reveal and correlate the shape of the growth interface with the observed anisotropic doping.

DC and analog/RF performance optimisation of source pocket dual work function TFET

ABSTRACTWe investigate a systematic study of source pocket tunnel field-effect transistor (SP TFET) with dual work function of single gate material by using uniform and Gaussian doping profile in the drain region for ultra-low power high frequency high speed applications. For this, a n+ doped region is created near the source/channel junction to decrease the depletion width results in improvement of ON-state current. However, the dual work function of the double gate is used for enhancement of the device performance in terms of DC and analog/RF parameters. Further, to improve the high frequency performance of the device, Gaussian doping profile is considered in the drain region with different characteristic lengths which decreases the gate to drain capacitance and leads to drastic improvement in analog/RF figures of merit. Furthermore, the optimisation is performed with different concentrations for uniform and Gaussian drain doping profile and for various sectional length of lower work function of the gate electrode. Finally, the effect of temperature variation on the device performance is demonstrated.

Voltage Reduction in Organic Light-Emitting Diodes by Sequential Deposition Doping

4,4’-N,N’-dicarbazolebiphenyl (CBP), a wide bandgap organicmaterialwith a lowglass transition temperature, was doped with WO3 or MoO3 through co-deposition and sequential deposition. The doping effects were studied via comparative characterization of hole-only devices and simple green organic light-emitting diodes. Doped films prepared by sequential deposition of alternative 0.5 nm oxide and 3–10 nm undoped CBP layers exhibited comparable or even higher conductivity than uniformly doped CBP prepared by co-deposition. Devices with a hole-transport layer of doped CBP had a turn-on voltage as low as 1 V and markedly improved lifetime compared to undoped devices. Secondary ionmass spectrometry revealed extensive intermixing in the sequentially deposited oxide/CBP structure, resulting in a nearly uniform doping profile with small concentration fluctuations. This paper demonstrated a simple and viable sequential deposition doping technique for organic semiconducting materials.

High quality boron-doped epitaxial layers grown at 200°C from SiF4/H2/Ar gas mixtures for emitter formation in crystalline silicon solar cells

Controlling the doping profile in solar cells emitter and front/back surface field is mandatory to reach high efficiencies. In the current state of the art, these doped layers are made by dopant diffusion at around 900°C, which implies potential temperature induced damages in the c-Si absorber and for which a precise control of doping is difficult. An alternative solution based on boron-doped epitaxial silicon layers grown by plasma-enhanced chemical vapor deposition (PECVD) from 200°C using SiF4/H2/Ar/B2H6 chemistry is reported. The structural properties of the doped and undoped epitaxial layers were assessed by spectroscopic ellipsometry (SE), high resolution transmission electron microscopy (HR-TEM) and X-ray diffraction (XRD). The incorporation of boron has been studied via plasma profiling time of flight mass spectrometry (PP-TOFMS) and secondary ion mass spectrometry (SIMS) measurements. The boron-doped epitaxial layers revealed excellent structural and electrical properties even for high carrier concentrations (>1019cm-3). Sheet resistances between 100 and 130 Ω/sq can been obtained depending on the thickness and the doping concentration, which is within the range of targeted values for emitters in c-Si solar cells. Electrochemical capacitance voltage (ECV) revealed a uniform doping profile around 3.1019 cm-3 and by comparing with SIMS measurement a doping efficiency around 50% has been found.

Validation of Fast Current Interruption Mechanism in Sub-Nanosecond High-Voltage Switching Diodes

The fast current interruption property of drift step recovery diodes (DSRDs) is utilized in high-voltage fast switches. Previously, using a physical device simulator, we have conducted a theoretical investigation of this mechanism in a p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> πn <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> structure and evaluated the expected dependence of device performances on its structure and driving conditions. In this letter, we experimentally validate these findings by presenting consistency between the theoretical results and the actual measured results. Diode structures with a uniform doping profile and abrupt junction were fabricated using thick layer epitaxy technology, which allows for improved control over the doping profile, compared with the traditional method of deep aluminum diffusion. The switching characteristics of the diodes were measured using a specially designed circuit. An outstanding switching time of 0.3 ns at 230 V per DSRD die was demonstrated by driving the diode with a reverse current density exceeding 1250 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . We conclude that a semi-empirical design of the diode and its driving conditions can be substituted by accurate modeling using the device simulator. By combining the physical understanding gained with accurate modeling capabilities and epitaxial growth technology, novel diode design and improved switching performance may be achieved.

DC and analogue/radio frequency performance optimisation of heterojunction double‐gate tunnel field‐effect transistor

The electrostatic behaviour of the different configurations of n-type heterojunction double-gate tunnel field-effect transistor (HDGTFET) has been analysed. The analysis is based on the basics of the circuit elements such as drain current, transconductance, parasitic capacitances, cut-off frequency and gain bandwidth product. From the investigation carried out, it can be inferred that dual metal hetero-dielectric double-gate HDGTFET with gate underlap achieves both low standby power OFF state current and high performance at low supply voltage. The performance of the device having different configurations has been analysed for drain region having a uniform and Gaussian doping profile.

The Influence of Doping on the Optoelectronic Properties of PbS Colloidal Quantum Dot Solids.

We report on an extensive spectroscopic investigation of the impact of substitutional doping on the optoelectronic properties of PbS colloidal quantum dot (CQD) solids. N-doping is provided by Bi incorporation during CQD synthesis as well as post-synthetically via cation exchange reactions. The spectroscopic data indicate a systematic quenching of the excitonic absorption and luminescence and the appearance of two dopant-induced contributions at lower energies to the CQD free exciton. Temperature-dependent photoluminescence indicates the presence of temperature-activated detrapping and trapping processes of photoexcitations for the films doped during and after synthesis, respectively. The data are consistent with a preferential incorporation of the dopants at the QDs surface in the case of the cation-exchange treated films versus a more uniform doping profile in the case of in-situ Bi incorporation during synthesis. Time-resolved experiments indicate the presence of fast dopant- and excitation-dependent recombination channels attributed to Auger recombination of negatively charged excitons, formed due to excess of dopant electrons. The data indicate that apart from dopant compensation and filling of dopant induced trap states, a fraction of the Bi ionized electrons feeds the QD core states resulting in n-doping of the semiconductor, confirming reported work on devices based on such doped CQD material.

Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping

In this paper, for the first time, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications. For this purpose, the suitability of the device for low-power applications is investigated by extracting the threshold voltage of the device using a transconductance change method and a constant current method. Furthermore, the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths. A highly doped layer is placed in the channel near the source–channel junction, and this decreases the width of the depletion region, which improves the ON-current ( ${I_{\rm{\scriptscriptstyle ON}}}$ ) and the RF performance. Furthermore, the circuit-level performance assessment is done by implementing a common source amplifier using the H-DGTFET; a 3-dB roll-off frequency of 230.11 GHz and a unity-gain frequency of 5.4 THz were achieved.

Dispersive Effects in Microwave AlGaN/AlN/GaN HEMTs With Carbon-Doped Buffer

Aluminium gallium nitride (AlGaN)/GaN high-electron mobility transistor performance is to a large extent affected by the buffer design, which, in this paper, is varied using different levels of carbon incorporation. Three epitaxial structures have been fabricated: 1) two with uniform carbon doping profile but different carbon concentration and 2) one with a stepped doping profile. The epitaxial structures have been grown on 4H-SiC using hot-wall metal–organic chemical vapor deposition with residual carbon doping. The leakage currents in OFF-state at 10 V drain voltage were in the same order of magnitude ( $10^{-4}$ A/mm) for the high-doped and stepped-doped buffer. The high-doped material had a current collapse (CC) of 78.8% compared with 16.1% for the stepped-doped material under dynamic $I$ – $V$ conditions. The low-doped material had low CC (5.2%) but poor buffer isolation. Trap characterization revealed that the high-doped material had two trap levels at 0.15 and 0.59 eV, and the low-doped material had one trap level at 0.59 eV.

Screen-Printed Si Paste for Localized B Doping in a Back Surface Field

In this letter, Si paste formed by p-type Si nanoparticles (NPs) and an organic solvent is used as the source of B. Si NPs with a diameter of $\sim 30$ nm are prepared using the pulsed electrical discharge method. The preprocessed Si wafers (after laser opening) are used as the substrate. Si paste with different percentages of Si NPs is screen-printed above the openings. B atoms diffuse into Si wafers through annealing. Uniform doping profiles are observed under a laser scanning microscope. The B doping is successful as evidenced by secondary ion mass spectroscopy.

Design of a 1200-V ultra-thin partial SOI LDMOS with n-type buried layer

A novel 1200-V ultra-thin partial silicon-on-insulator (PSOI) lateral double-diffusion metal oxide semiconductor (LDMOS) with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed in this paper. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conduction region for majority carriers and a silicon window to improve self-heating effect (SHE). A combination of uniform and linear variable doping (ULVD) profile is utilized in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (Ron,sp) and breakdown voltage (BV). With the n-drift region length of 80μm, the NBL PSOI LDMOS obtains a high BV of 1243V which is improved by around 105V in comparison to the conventional SOI LDMOS with linear variable doping (LVD) profile for the n-drift region (LVD SOI LDMOS). Besides, the 1200-V NBL PSOI LDMOS has a lower maximum temperature (Tmax) of 333K at a power (P) of 1mW/μm which is reduced by around 61K. Meanwhile, Ron,sp and Tmax of the NBL PSOI LDMOS are lower than those of the conventional LVD SOI LDMOS for a wide range of BV.

Configurable Logic Gates Using Polarity-Controlled Silicon Nanowire Gate-All-Around FETs

This work demonstrates the first fabricated 4-transistor logic gates using polarity-configurable, gate-all- around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of free- dom of dynamic polarity control (n or p-type). In addition, devices are fabricated with low, uniform doping profiles, reducing constraints at scaled technology nodes. We demonstrate through measurements and simulations how this technology can be applied to fabricate logic gates with fewer resources than CMOS. Specifically, full-swing output XOR and NAND logic gates are demonstrated using the same physical 4-transistor circuit.