Underlap DG MOSFET Research Articles

Subthreshold Current and Swing Modeling of Gate Underlap DG MOSFETs with a Source/Drain Lateral Gaussian Doping Profile

This paper proposes a new model for the subthreshold current and swing of the short-channel symmetric underlap ultrathin double gate metal oxide field effect transistors with a source/drain lateral Gaussian doping profile. The channel potential model already reported earlier has been utilized to formulate the closed form expression for the subthreshold current and swing of the device. The effects of the lateral straggle and geometrical parameters such as the channel length, channel thickness, and oxide thickness on the off current and subthreshold slope have been demonstrated. The devices with source/drain lateral Gaussian doping profiles in the underlap structure are observed to be highly resistant to short channel effects while improving the current drive. The proposed model is validated by comparing the results with the numerical simulation data obtained by using the commercially available ATLAS™, a two-dimensional (2-D) device simulator from SILVACO.

Effects of Elevated Source/Drain and Side Spacer Dielectric on the Drivability Optimization of Non-abrupt Ultra Shallow Junction Gate Underlap DG MOSFETs

The effects of drain/source elevation height (hSD) and side spacer dielectric between the gate and source/drain regions on the drivability performance of the non-abrupt ultra-shallow-junction gate underlap double gate metal oxide field effect transistor of 18 nm gate length has been investigated in terms of the on-state (Ion), off-state (Ioff) drain currents, and Ion/Ioff ratio. Among the Air, SiO2, Si3N4, and HfO2 used as spacer dielectrics, while both Ion and Ion/Ioff are increased with the elevation height (hSD) and permittivity of the spacer dielectric, interestingly, an inverse relation between the Ion and Ioff for all hSD below ∼32.5 nm is observed only for the SiO2 spacer dielectric. Another new observation is the increase in Ioff with the hSD and permittivity of the spacer dielectric due to the enhancement of gate-induced drain leakage current owing to the increased vertical electric field at the drain side. For the most commonly used dielectrics SiO2 and HfO2 in the spacer region, the Ion/Ioff ratio is increased by ∼277% (at hSD = 32.5 nm) and ∼516% (at hSD = 9.5 nm) with respect to their corresponding values at zero elevation, respectively.

Analysis of high-k spacer on symmetric underlap DG-MOSFET with Gate Stack architecture

This paper shows the systematic study of underlap double gate (U-DG) NMOSFETs with Gate Stack (GS) under the influence of high-k spacers. In highly scaled devices, underlap is used at the Source and Drain side so as to reduce the short channel effects (SCE’s), however, it significantly reduces the on current due to the increased channel resistance. To overcome these drawbacks, the use of high-k spacers is projected as one of the remedies. In this paper, the analog performance of the devices is studied on the basis of parameters like transconductance (gm), transconductance generation factor (gm/Id) and intrinsic gain (gmro). The RF performance is analyzed on the merits of intrinsic capacitance (Cgd, Cgs), resistance (Rgd, Rgs), transport delay (τm), inductance (Lsd), cutoff frequency (fT), and the maximum frequency of oscillation (fmax). The circuit performance of the devices are studied by implementing the device as the driver MOSFET in a Single Stage Common Source Amplifier. The Gain Bandwidth Product (GBW) has been analyzed from the frequency response of the circuit.

Analytical Modeling of Potential Distribution and Threshold Voltage of Gate Underlap DG MOSFETs with a Source/Drain Lateral Gaussian Doping Profile

This paper reports a new two-dimensional (2D) analytical model for the potential distribution and threshold voltage of the short-channel symmetric gate underlap ultrathin DG MOSFETs with a lateral Gaussian doping profile in the source (S)/drain (D) region. The parabolic approximation and conformal mapping techniques have been explored for solving the 2D Poisson’s equation to obtain the channel potential function of the device. The effects of straggle parameter (of the lateral Gaussian doping profile in the S/D region), underlap length, gate length, channel thickness and oxide thickness on the surface potential and threshold voltage have been investigated. The loss of switching speed due to the drain-induced barrier lowering (DIBL) has also been reported. The proposed model results have been validated by comparing them with their corresponding TCAD simulation data obtained by using the commercially available 2D ATLAS™ simulation software.

Impact of lateral straggle on analog and digital circuit performance using independently driven underlap DG-MOSFET

In this work, the effect of lateral straggle on independently driven underlap double gate MOSFET (IDUDGMOS) is presented based on analog and digital circuit performances. The lateral straggle in IDUDGMOS devices is due to process induced source/drain out diffusion and it varies the desired device characteristics. For the analysis of this variation on circuit performance of the device, an Amplitude Modulator (AM) circuit and a SRAM circuit is considered for analog and digital circuit application considerations respectively. For the analysis of the device in AM circuit the parameters studied are the bandwidth, the gain and the linearity, correspondingly for SRAM circuit the parameters studied are the Static Noise Margin (SNM) and the circuit delay. The analysis of the AM circuit designed using the IDUDGMOS suggested that the power loss and the bandwidth of the circuit degrade with increasing lateral straggle. For the SRAM circuit the analysis suggests that larger straggle lengths in the device results in reduced time delay but, the SNM is smaller as well.

RF parameter extraction of underlap DG MOSFETs: a look up table based approach

In this study, a look up table (LUT) is developed to extract the intrinsic RF parameters of underlap DG MOSFET (UDG-MOSFET) including the non-quasi-static (NQS) effect. The LUT-based approach proposed; can accurately extract complex RF parameters of UDG-MOSFET under different bias conditions, necessary for RF circuit simulations by an interpolation algorithm. The RF parameters including intrinsic gate to drain capacitance (C gd), gate to source capacitance (C gs), gate to drain resistance (R gd), gate to source resistance (R gs), gate to source transconductance (gm ), drain to source transconductance (g ds), transport delay (τm ), capacitance because of DIBL (C sdx) and inductance because of transport delay (L sd), cut-off frequency (f T) and maximum frequency of oscillation (f max) are extracted using LUT approach. Parameters extracted using LUT are compared with simulated data, considering the NQS effect, and are found in good agreement. For RF circuit applications a low-noise amplifier is designed, with the UDG-MOSFET, operating at a tuned frequency of 10 GHz.

Effect of Source/Drain Lateral Straggle on Distortion and Intrinsic Performance of Asymmetric Underlap DG-MOSFETs

This paper presents a systematic study of the effect of source/drain (S/D) implant lateral straggle on the RF performance of the symmetric and asymmetric underlap double gate (UDG) MOSFET devices. The length of the underlap regions ( L \({}_{un}\) ) on each side of the gate is a critical technology parameter in determining the performance of UDG-MOSFETs. However, the value of L \({}_{un}\) is susceptible to variation due to S/D implant lateral diffusion. Therefore, it is critical to investigate the impact of S/D implant lateral straggle on the performance of UDG-MOSFETs. This paper shows that the improvement in the RF performance of the UDG-MOSFETs over the conventional DG-MOSFETs can be achieved by optimizing the S/D lateral straggle of the asymmetric UDG-MOSFETs. The RF performance study includes intrinsic capacitances and resistances, transport delay, inductance, and the cut-off frequency.

Study of body and oxide thickness variation on analog and RF performance of underlap DG-MOSFETs

The underlap double gate MOSFET (UDG-MOSFET) has been well established as a potential candidate for the RF applications. However, before implementation the various process related variations are required to be addressed for the better dependability. In this paper, the effect of process dependent parameter variations on the RF performance of the UDG-MOSFET is analyzed. The process dependent parameters considered are the oxide and the body thicknesses. The RF performance of UDG-MOSFET is analyzed as a function of RF figure of merits (FOMs), intrinsic capacitance (Cgs, Cgd), intrinsic resistance (Rgs, Rgd), transport delay (τm), inductance (Lsd) and analog FOMs transconductance (gm), transconductance generation factor (gm/Id), output resistance (Ro) and intrinsic gain (gmRo). The analysis is performed using the non-quasi static (NQS) small signal model of the UDG-MOSFET.

Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer

In analog and RF circuit applications Harmonic distortion (HD) is an important reliability issue that arises due to non-linear performance of devices. In this paper, the asymmetric underlap double gate MOSFET (AUDG-MOSFET) is analyzed for the HD with high-k spacers. In this analysis the devices are compared for their primary distortion components designated by the second order distortion (HD2), the third order distortion (HD3) and the total harmonic distortion (THD). The distortion characteristics of the device are studied as a function of the gate voltage (Vgs) and the transconductance generation factor (gm/Id) considering the influence of drain current (Id) and the transconductance (gm). A significant improvement on the HD of the device by using high-k spacers is inferred, thereby ascertaining better reliability for RF applications. In addition to this, the distortion in the output characteristics of Cascode and differential amplifier circuits designed with AUDG-MOSFET device is also analyzed in detail.

Performance assessment of gate material engineered AlInN/GaN underlap DG MOSFET for enhanced carrier transport efficiency

In the work proposed, performance of dual material gate (DMG) AlInN/GaN underlap DG MOSFET has been analyzed and compared with the corresponding performance of single material gate (SMG) AlInN/GaN underlap DG MOSFET using Sentaurus TCAD device simulation. A systematic, quantitative investigation of key device metrics for DMG–DG device is presented and a comparison with SMG–DG device is done for a wide range of gate and underlap lengths. The key idea in this paper is to demonstrate the improved performance exhibited by DMG–DG device over SMG–DG device, due to enhanced carrier transport efficiency and suppressed short channel effect (SCE). Simulation reveals an improvement in drain current, drain induced barrier lowering (DIBL), Ion/Ioff, Delay and Energy Delay Product (EDP) for DMG–DG MOSFET as compared to SMG–DG MOSFET. Very high drain current of 6.7mA/μm, low DIBL of 1.62mV/V, high Ion/Ioff ratio of 4.044e107, low delay of 0.001ps and low EDP of 1.37e−31Js/μm are obtained for DGM–DG device. However, subthreshold slope (SS) for DMG–DG device is on higher side than SMG–DG. The proposed AlInN/GaN Heterostructure Underlap DGM–DG MOSFET shows excellent promise as one of the candidates to substitute present MOSFET for future high speed applications.

Influence of barrier thickness on AlInN/GaN underlap DG MOSFET device performance

We have investigated the influence of Al0.83In0.17N barrier layer thickness (TB) on device performance of 18nm gate length ultra thin body AlInN/GaN heterostructure underlap DG MOSFET, using 2D Sentaurus TCAD simulation. Hydrodynamic model used in the simulation is validated with previously published experimental results. Simulation of major device performance parameters such as DIBL, SS, Delay, Vt, ION and energy delay product have been done for TB ranging from 0nm to 4nm. A comprehensive, quantitative investigation of key analog and RF figures-of-merits such as gm, gm/Id, Ro, fT and fmax is also done. As TB increases the drain current increases and delay decreases, but at the expense of loss of electrostatic control leading to increased short channel effect i.e. higher DIBL and SS. Also, negative shift in threshold voltage is observed for rising TB. As TB reduces, increase in Cgg,gm, gm/Id and Ro is noticed due to decrease in separation between the gate and channel, leading to enhanced gate control. Improvement in both fT and fmax with reduction in TB was noticed, with the peak values of 668GHz and 312GHz respectively. There is tradeoff between achieved drain current, and the device electrostatic control for varying TB. Selection of appropriate TB is of vital significance as it determines the device performance.

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (Vt), Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the Ioff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

Comparative assessment of III–V heterostructure and silicon underlap double gate MOSFETs

Comparative assessment of III–V heterostructure and silicon underlap DG-MOSFETs, is done using 2D Sentaurus TCAD simulation. III–V heterostructure device has narrow-band In0.53Ga0.47As and wide-band InP layers for body, and high-K gate dielectric. Density gradient model is used for simulation and interface traps are considered. Benchmarking of simulation results show that III–V device provides higher on current, lesser delay, lower energy-delay product and lower DIBL than silicon device. However III–V device has higher SS and lower Ion/Ioff than silicon device. The results indicate that there is a need to optimize the Ion/Ioff, SS and DIBL values for specific circuits.

Investigation of asymmetric effects due to gate misalignment, gate bias and underlap length in III–V heterostructure underlap DG MOSFET

In the present work, we investigate the influence of asymmetry in III–V heterostructure underlap DG MOSFET caused by back gate movement, back gate voltages and drain side underlap length. The device has narrowband In0.53Ga0.47As and wideband InP layers in the channel, along with high-K Al2O3 as the gate dielectric. The 2D Sentaurus TCAD simulations are done using drift diffusion model and interface traps are considered. The simulation model is calibrated with the previous reported experimental results. For the same gate misalignment value, back gate shift toward drain (BG_D) resulted in a lower DIBL, Ioff and Delay, than back gate shift towards source (BG_S). Conversely, BG_S results in lower SS, higher Ion and Ion/Ioff ratio. Excellent threshold voltage controllability, reduced delay, reduced energy delay product, higher Ion/Ioff ratio are achieved by varying back gate voltage. Varying drain underlap reduces DIBL, SS, Delay, Ioff and increases Vt and Ion/Ioff ratio. Thus, application specific optimized device parameters can be achieved with asymmetrical device structure, asymmetrical gate bias or its combination.

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied–independent gate and symmetric–asymmetric options

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.

Nonclassical Channel Design in MOSFETs for Improving OTA Gain-Bandwidth Trade-Off

In this paper, gain-bandwidth (GB) trade-off associated with analog device/circuit design due to conflicting requirements for enhancing gain and cutoff frequency is examined. It is demonstrated that the use of a nonclassical source/drain (S/D) profile (also known as underlap channel) can alleviate the GB trade-off associated with analog design. Operational transconductance amplifier (OTA) with 60 nm underlap S/D MOSFETs achieve 15 dB higher open loop voltage gain (AVO_OTA) along with three times higher cutoff frequency (fT_OTA) as compared to OTA with classical nonunderlap S/D regions. Underlap design provides a methodology for scaling analog devices into the sub-100 nm regime and is advantageous for high temperature applications with OTA, preserving functionality up to 540 K. Advantages of underlap architecture over graded channel (GC) or laterally asymmetric channel (LAC) design in terms of GB behavior are demonstrated. Impact of transistor structural parameters on the performance of OTA is also analyzed. Results show that underlap OTAs designed with spacer-to-straggle (s/ σ) ratio of 3.2 and operated below a bias current (IBIAS) of 80 μA demonstrate optimum performance. The present work provides new opportunities for realizing future ultra wide band OTA design with underlap DG MOSFETs in silicon-on-insulator (SOI) technology.