Influence of barrier thickness on AlInN/GaN underlap DG MOSFET device performance

Abstract

We have investigated the influence of Al0.83In0.17N barrier layer thickness (TB) on device performance of 18nm gate length ultra thin body AlInN/GaN heterostructure underlap DG MOSFET, using 2D Sentaurus TCAD simulation. Hydrodynamic model used in the simulation is validated with previously published experimental results. Simulation of major device performance parameters such as DIBL, SS, Delay, Vt, ION and energy delay product have been done for TB ranging from 0nm to 4nm. A comprehensive, quantitative investigation of key analog and RF figures-of-merits such as gm, gm/Id, Ro, fT and fmax is also done. As TB increases the drain current increases and delay decreases, but at the expense of loss of electrostatic control leading to increased short channel effect i.e. higher DIBL and SS. Also, negative shift in threshold voltage is observed for rising TB. As TB reduces, increase in Cgg,gm, gm/Id and Ro is noticed due to decrease in separation between the gate and channel, leading to enhanced gate control. Improvement in both fT and fmax with reduction in TB was noticed, with the peak values of 668GHz and 312GHz respectively. There is tradeoff between achieved drain current, and the device electrostatic control for varying TB. Selection of appropriate TB is of vital significance as it determines the device performance.