Performance assessment of gate material engineered AlInN/GaN underlap DG MOSFET for enhanced carrier transport efficiency

Abstract

In the work proposed, performance of dual material gate (DMG) AlInN/GaN underlap DG MOSFET has been analyzed and compared with the corresponding performance of single material gate (SMG) AlInN/GaN underlap DG MOSFET using Sentaurus TCAD device simulation. A systematic, quantitative investigation of key device metrics for DMG–DG device is presented and a comparison with SMG–DG device is done for a wide range of gate and underlap lengths. The key idea in this paper is to demonstrate the improved performance exhibited by DMG–DG device over SMG–DG device, due to enhanced carrier transport efficiency and suppressed short channel effect (SCE). Simulation reveals an improvement in drain current, drain induced barrier lowering (DIBL), Ion/Ioff, Delay and Energy Delay Product (EDP) for DMG–DG MOSFET as compared to SMG–DG MOSFET. Very high drain current of 6.7mA/μm, low DIBL of 1.62mV/V, high Ion/Ioff ratio of 4.044e107, low delay of 0.001ps and low EDP of 1.37e−31Js/μm are obtained for DGM–DG device. However, subthreshold slope (SS) for DMG–DG device is on higher side than SMG–DG. The proposed AlInN/GaN Heterostructure Underlap DGM–DG MOSFET shows excellent promise as one of the candidates to substitute present MOSFET for future high speed applications.