Um Technology Research Articles

단일 입력 직렬 통신을 이용한 퓨즈 제어 회로 설계 및 구현

In this paper, we propose a fuse controller which is used for storing the optimal value or the correction value for the surrounding product of the IoT applications and it is implemented serial communication circuit using a single pin. Because of the proposed single pin protocol is simpler in the hardware than the conventional and SPI using two or more pins, it is suitable for the area of small amount of data transmission. The function of the one pin protocol is verified by logic simulation and the FPGA test board and it is fabricated using CMOS 0.35um technology. It is expected to use the IoT product that require the low power consumption and simple hardware.

HEVC/VP9 4×4 Transform 통합 블록 설계

본 논문에서는 HEVC와 VP9 코덱의 계수 변환 (Transform)을 수행하는 통합형 아키텍쳐를 제안하여 하드웨어 크기를 줄이고자 한다. 제안하는 아키텍쳐는 HEVC <TEX>$4{\times}4$</TEX> IDCT, HEVC <TEX>$4{\times}4$</TEX> IDST, VP9 <TEX>$4{\times}4$</TEX> IDCT, VP9 <TEX>$4{\times}4$</TEX> IADST를 통합 하드웨어에서 처리가 가능하다. HEVC <TEX>$4{\times}4$</TEX> IDCT와 VP9 <TEX>$4{\times}4$</TEX> IDCT는 계수의 스케일만 다를 뿐 동일한 IDCT 연산을 사용하며, 마찬가지로 HEVC <TEX>$4{\times}4$</TEX> IDST와 VP9 <TEX>$4{\times</TEX><TEX>}4$</TEX> IADST도 계수의 스케일만 다를 뿐 동일한 IDST 연산을 사용한다. 더욱이 IDCT 연산과 IDST 연산에는 상당히 많은 유사점이 있어 일부 하드웨어를 공동으로 사용할 수 있다. 따라서 제안하는 하드웨어는 4가지 연산에 대해 곱셈기의 계수는 각각 다르지만 버터플라이 덧셈기등은 공통으로 사용하여 통합적으로 수행한다. 0.18um 공정에서 합성했을 때 게이트 수가 약 6,679 게이트로 기존 아키텍처 대비 25.3% 감소함을 확인하였다. This paper proposes a unified <TEX>$4{\times}4$</TEX> transform architecture for HEVC and VP9 codec to reduce hardware size. It performs HEVC <TEX>$4{\times}4$</TEX> IDCT, HEVC <TEX>$4{\times}4$</TEX> IDST, VP9 <TEX>$4{\times}4$</TEX> IDCT, and VP9 <TEX>$4{\times}4$</TEX> IADST in a unified hardware. HEVC <TEX>$4{\times}4$</TEX> IDCT and VP9 <TEX>$4{\times}4$</TEX> IDCT have same IDCT computation except for the scales of coefficients. Similarly, HEVC <TEX>$4{\times}4$</TEX> IDST and VP9 <TEX>$4{\times}4$</TEX> IADST have same IDST computation except for the scales of coefficients. Furthermore, IDCT and IDST have quite a lot of similarity, so they can share some hardwares in common. So the proposed hardware performs all 4 operations in a unified hardware, where each operation has its own multiplication coefficients with shared butterfly adders. The synthesized block in 0.18 um technology is 6,679 gates, and the gate count is reduced by 25.3% in comparison with conventional designs.

HEVC CABAC 문맥 모델러의 하드웨어 구현

CABAC은 문맥 기반 적응적 이진 산술 부호화 방식으로, 이전까지 부호화 된 심볼들의 정보를 이용하여 확률을 업데이트하여 부호화 효율을 높이는 기법이다. 문맥 모델러는 통계적 상관성을 고려하여 심볼에 따라 확률 모델을 설계하는 CABAC의 핵심 블록으로서, 본 논문에서는 문맥 모델러의 효율적인 하드웨어 아키텍쳐를 제안한다. Verilog HDL로 기술되어 0.18 um 공정으로 설계된 문맥 모델러는 메모리를 포함하여 29,832개의 게이트로 이루어져 있으며, 최대 동작속도는 200 MHz, 최대 처리율은 200 Mbin/s이다. CABAC is a context-based adaptive binary arithmetic coding method. It increases the encoding efficiency by updating the probability based on the information of the previously coded symbols. Context modeler is a core block of CABAC, which designs a probability model according to the symbol considering statistical correlations. In this paper, an efficient hardware architecture of CABAC context modeler is proposed. The proposed context modeler was designed in Verilog HDL and it was implemented in 0.18 um technology. Its gate count is 29,832 gates including memory. Its operating speed and throughput are 200 MHz and 200 Mbin/s, respectively.

FRACTAL GEOMETRIES IN LATERAL FLUX CAPACITOR DESIGN – EXPERIMENTAL RESULTS

Capacitance density is increased when lateral flux structures are used in CMOS technologies compared to classic parallel-palate capacitors. Lateral-flux capacitors where designed based on three different fractal geometries. Capacitors are designed with and without special MMC metal layer available in some CMOS technologies for capacitor design. For theoretical analysis verification a special ASIC has been designed and fabricated in UMC 0.18um technology. Presented result are obtained by measurement of 5 ICs. Some capacitor structures have much higher capacitance density than classic parallel-plates capacitor without&nbsp; MMC layer. Few presented structures have higher capacitance density than parallel-plate capacitor made with MMC layer. Capacitors have small process parameters spread.

움직임 감지를 사용하여 영상 해상도를 자동 제어하는 실시간 다중 카메라 영상 감시 시스템의 구현

본 논문에서는 움직임 감지를 사용하여 영상 해상도를 자동 제어하는 실시간 다중 카메라 영상 감시 시스템을 구현하였다. 평상시에는 4개 채널의 영상을 QVGA급으로 취득한 후 하나의 VGA급 영상으로 통합하여 전송한다. 움직임이 포착되는 경우에는 해당 채널의 영상을 자동으로 확대하여 VGA급으로 취득한 후 나머지 3개 채널의 영상을 QQVGA급으로 줄여서 오버레이한다. 이를 통하여 모든 채널의 영상을 놓치지 않으면서도 전송 대역폭을 늘리지 않고 움직임이 포착된 채널을 확대하여 감시할 수 있다. 0.18 um 공정에서 합성한 최대 동작 주파수는 110 MHz로서 이론상으로 4개의 HD급 카메라를 지원할 수 있다. This paper proposes a real-time multi-camera video surveillance system with automatic resolution control using motion detection. In ordinary times, it acquires 4 channels of QVGA images, and it merges them into single VGA image and transmit it. When motion is detected, it automatically increases the resolution of motion-occurring channel to VGA and decreases those of 3 other channels to QQVGA, and then these images are overlaid and transmitted. Thus, it can magnifies and watches the motion-occurring channel while maintaining transmission bandwidth and monitoring all other channels. When it is synthesized with 0.18 um technology, the maximum operating frequency is 110 MHz, which can theoretically support 4 HD cameras.

A Combined Approach of IVC and GR for Leakage Power Reduction in CMOS VLSI Digital Circuit

In Deep Sub-Micron (DSM) technology, leakage power dissipation consumes the substantial percentage of the total power dissipation and rises exponentially according to the International Technology Roadmap for Semiconductor (ITRS). Leakage power decreases battery life for the entire portable battery operated device such as mobile phones, laptop and cam coder etc. VLSI design constraints are always area, power and delay. To reduce the leakage power losses several techniques has been proposed that proficiently reduces leakage power dissipation Leakage power in CMOS VLSI circuits can be controlled at the circuit level. This paper has considered two run time leakage reduction mechanics i.e. Input Vector Control (IVC) and Gate Replacement (GR). When the first technique is applied on the CMOS circuit, 30% average leakage power reduction is achieved where as 46% of average leakage power is reduces due to GR technique. The Maximum leakage reduction is achieved of 41.2% and 73% due to IVC and GR techniques respectively. These techniques have been applied on ISCAS benchmark circuit C17 using TSMC0.18um technology file on HSPICE simulator.

태양광 분산형 최대전력점 추적 제어를 위한 고전압 게이트 드라이버 설계

본 논문에서는 태양광시스템의 분산형 최대 전력점 추적(DMPPT)을 제어하는 게이트 드라이버 회로를 설계하였다. 그림자가 생긴 모듈에서도 최대 전력점을 추적할 수 있는 분산형 방식(DMPPT) 방식을 구현 하였으며, 각각의 모듈 내부에 DC-DC 변환기를 구동하기 위한 고전압 게이트 구동회로를 설계하였다. 태양광 시스템의 내부는 12비트 ADC, PLL, 게이트 드라이버가 내장 되어 있다. 게이트 드라이버의 하이 사이드 레벨 쉬프터에 숏-펄스 발생기를 추가하여 전력소모와 소자가 받는 스트레스를 줄였다. BCDMOS 0.35um 공정을 사용하여 구현하였으며 최대 2A 전류를 감달 할 수 있고, 태양 광 전압 최대 50V까지 받을 수 있도록 설계하였다. This paper describes the design of gate driver circuits in distributed maximum power point tracking(DMPPT) controller for photovoltaic system. For the effective DMPPT control in the existence of shadowed modules, high voltage gate driver is applied to drive the DC-DC converter in each module. Some analog blocks such as 12-b ADC, PLL, and gate driver are integrated in the SoC for DMPPT. To reduce the power consumption and to avoid the high voltage damage, a short pulse generator is added in the high side level shifter. The circuit was implemented with BCDMOS 0.35um technology and can support the maximum current of 2A and the maximum voltage of 50V.

센서시스템에서의 저전력 비동기 설계를 위한 인터페이싱 회로

센서 시스템과 같은 저전력 설계를 요구하는 시스템에서 기존의 동기방식의 회로는 낮은 전압에서 지연(delay)이 급격히 증가하여 시스템의 전체 성능을 유지할 수 없을 뿐만 아니라, 공정, 전압, 온도 변이 (PVT variation), 노화 등에 크게 영향을 받아서 올바른 동작을 기대할 수 없다. 따라서, 신뢰할 수 있는 초저전력 설계에서 비동기 회로가 스케일링 이슈를 해결할 수 있는 방법으로 최근 다시 고려되고 있다. 그러나, 디지털 시스템에서 동기회로를 NCL 회로로 모두 대체하는 것은 쉽지가 않기때문에 동기회로와 비동기 회로 사이의 연결이 꼭 필요하다. 본 논문에서는 동기회로와 비동기 회로를 연결할 수 있는 새로운 설계방법을 보이고, 0.18um 공정기술을 사용한 <TEX>$4{\times}4$</TEX> 곱셈기를 사용해서 검증을 하였다. Conventional synchronous circuits in low power required systems such as sensor systems cannot only satisfy the timing requirement of the low voltage digital systems, but also they may generate wrong outputs under the influence of PVT variations and aging effects. Therefore, in the reliable ultra-low power design, asynchronous circuits have recently been reconsidered as a solution for scaling issues. However, it is not easy to totally replace synchronous circuits with asynchronous circuits in the digital systems, so the interfacing between the synchronous and asynchronous circuits is indispensable for the digital systems. This paper presents a new design for interfacing between asynchronous circuits and synchronous circuits, and the interface circuits are applied to a <TEX>$4{\times}4$</TEX> multiplier logic designed using 0.11um technology.

Design of a Fast JND Algorithm Based on Discrete Wavelet Transform and its VLSI Implementation

The computation of JND is very complex, which makes it difficult to embed it into integrated circuits. To solve this problem, Haar-DWT based JND model is exploited and its corresponding pipeline architecture is developed in this paper. To evaluate its performance, the architecture is modeled with hardware description language, and implemented by SMIC 0.18um technology. The area of JND core is 42052 gates, which is significantly smaller than the full band JND based architecture. From the experiment results, the system goes on well at 161 MHz and achieves 78% time saving compared with the full band JND based architecture.

저면적 HEVC 코어 변환기 아키텍쳐 설계

This paper proposes and implements an core transform architecture, which is one of the major processes in HEVC video compression standard. The proposed core transform architecture is implemented with only adders and shifters instead of area-consuming multipliers. Shifters in the proposed core transform architecture are implemented in wires and multiplexers, which significantly reduces chip area. Also, it can process from to blocks with common hardware by reusing processing elements. Designed core transform architecture in 0.13um technology can process a block with 2-D transform in 130 cycles, and its gate count is 101,015 gates.

Comparative study of different Sense Amplifiers in 0.18um technology

A comparative study of different types of sense amplifiers [1] using 0.18um technology is presented. The sense amplifiers under considerations are used in SRAM and DRAM cells.The sensing delay of different types of sense amplifiers are evaluated with respect to variation of bitline capacitance. Comparative results are also provided for the variation in delay with respect to power supply. Extensive results based on 0.18um CMOS technology using CADENCE Spectre simulation tools are presented for different architectures of sense amplifiers. From these results it has been proven that if the output of sense amplifier is isolated from the bitline parasitic capacitance then the sensing delay of sense amplifier reduces.

Striation-Formation during Oxide Plasma-Etch for a 0.35um Technology

not Available.

MPPT 제어기능을 갖는 빛과 진동 에너지를 이용한 에너지 하베스팅 회로 설계

본 논문에서는 초소형 센서노드를 위한 MPPT(Maximum Power Point Tracking) 제어기능을 갖는 빛과 진동 에너지를 이용한 에너지 하베스팅 회로를 설계하였다. 설계된 회로는 MPPT 제어를 통해 온칩 솔라 셀과 압전소자로부터 최대 가용 전력을 수확하고, 수확된 에너지를 저장 커패시터에 병합하여 저장한다. 병합된 에너지는 PMU(Power Management Unit)를 통해 센서노드로 공급된다. MPPT 제어는 변환소자의 개방전압과 MPP 전압간의 비례관계를 이용하여 구현하였다. 제안된 회로는 0.18um CMOS 공정으로 설계하였으며, 모의실험을 통해 동작을 검증하였다. 설계된 에너지 하베스팅 회로와 온칩 솔라 셀의 칩 면적은 각각 <TEX>$2.85mm^2$</TEX>와 <TEX>$8mm^2$</TEX>이다. This paper describes an energy harvesting circuit using solar and vibration energy with MPPT(Maximum Power Point Tracking) control for micro sensor nodes. The designed circuit employs MPPT control to harvest maximum power available from a PZT vibration element and an integrated solar cell. The harvested energies are simultaneously combined and stored in a storage capacitor, and then managed and transferred into sensor node by PMU(Power Management Unit). MPPT controls are implemented using the linear relationship between the open-circuit voltage of an energy transducer and its MPP(Maximum Power Point) voltage. The proposed circuit is designed in a CMOS 0.18um technology and its functionality has been verified through extensive simulations. The designed energy harvesting circuit and integrated solar cell occupy <TEX>$2.85mm^2$</TEX> and <TEX>$8mm^2$</TEX> respectively.

An Efficient Reconfigurable Filter Design for Reducing Dynamic Power

This paper presents an architectural view of designing a digital filter. The main idea is to design a reconfigurable filter for reducing dynamic power consumption. By considering the input variation’s we reduce the order of the filter considering the coefficient are fixed. The filter is implemented using mentor graphics using TSMC .18um technology. The power consumption is decreased in the rate of 16% from the conventional model with a slight increase in area overhead. If the filter coefficients are fixed then the power can be reduced up to 18% and the area overhead can also be reduced from the reconfigurable architecture. Key words— Low power digital filter, Reconfigurable filter.

Low Cost Design of a Hybrid Architecture of Integer Inverse DCT for H.264, VC‐1, AVS, and HEVC

The paper presents a unified hybrid architecture to compute the 8 × 8 integer inverse discrete cosine transform (IDCT) of multiple modern video codecs—AVS, H.264/AVC, VC‐1, and HEVC (under development). Based on the symmetric structure of the matrices and the similarity in matrix operation, we develop a generalized “decompose and share” algorithm to compute the 8 × 8 IDCT. The algorithm is later applied to four video standards. The hardware‐share approach ensures the maximum circuit reuse during the computation. The architecture is designed with only adders and shifters to reduce the hardware cost significantly. The design is implemented on FPGA and later synthesized in CMOS 0.18 um technology. The results meet the requirements of advanced video coding applications.

Low noise front end ICECAL ASIC for the upgrade of the LHCb calorimeter

A fully differential ASIC with cooled input termination is presented as a solution for the Upgrade of the Calorimeter front end electronics. The LHCb experiment needs to increase about ten times the integrated luminosity in order to study new physics. The increase in signal has to be compensated reducing the gain of the photomultipliers which implies stringent noise requirements. The proposed solution offers an active termination at the input and avoids the noise originated by the use of a resistor. The circuit is based on a two interleaved channel with a first amplifier stage, a switched integrator, and a Track-and-Hold. Two prototypes have been implemented and tested in SiGe BiCMOS 0.35um technology.

스코어 버스 중재방식의 설계 및 성능 분석

버스 시스템은 하나의 버스 내에 여러 개의 마스터와 슬레이브, 아비터 그리고 디코더로 구성되어 있다. 마스터는 CPU, DMA, DSP 등과 같은 데이터의 명령을 수행하는 프로세서를 말하며, 슬레이브는 SRAM, SDRAM, 레지스터 등과 같이 명령에 응답하는 메모리를 말한다. 또한 아비터는 마스터가 동시간대에 버스를 이용할 수 없기 때문에 이를 중재하는 역할을 수행하는데, 어떠한 중재 방식을 선택하는가에 따라 버스 시스템의 성능이 크게 바뀔 수 있다. 일반적인 중재 방식에는 fixed priority 방식, round-robin 방식이 있으며, 이를 개선한 TDMA 방식과 Lottery bus 방식 등이 현재까지 제안되었다. 본 논문에서는 새로운 중재 방식인 스코어 중재 방식을 제안하고 RTL 디자인후 하이닉스 0.18um 공정 라이브러리를 이용하여 설계 합성하였으며, 일반적인 중재방식과 시뮬레이션을 통해 성능을 비교 분석하였다. Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method, bus system performance can be changed definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this study, we proposed the score arbitration method and synthesized it using Hynix 0.18um technology, after design of RTL. Also we analyze the performance compared with general arbitration methods through simulation.

Power Comparison of CMOS and Adiabatic Full Adder Circuits

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.

Characterization of Random Telegraph Signal Effects for 0.18um Technology

The paper gives a summary of RTS noise data captured from 0.18um technology. It can be a reference for the channel area and voltage bias selection for RTS measurement.

Voltage Controlled Ring Oscillator for Low Phase Noise Application

design for a voltage-controlled ring oscillator (VCO) is presented. The design allows an implementation of low frequency ring oscillator using relatively small devices and less stage. It is implemented using .18um technology provided by TSMC technology using 3.3V power supply. The VCO topology exhibits a very wide tuning range from few Hz to 368.9 MHz. It also features the rapid voltage swing and the 48% duty cycle with good transient characteristics which is difficult to get from the conventional oscillator. Its power dissipation at the maximum oscillation frequency is 35.05 mW. A frame work for modeling the phase noise in complementary metal-oxide-semiconductor (CMOS) ring oscillators. Phase noise for simulated circuit is -88dbc when offset frequency is 10 5 HZ.