Um Technology Research Articles

IC Bond Pad Structural Study by “Ripple Effect”

IC bond pad structural reliability is studied for a variety of experimental pad designs in a 0.18um technology, having patterned metallization to simulate bond-over-active-circuitry (BOAC) situations in top-metal-minus-one and below. Underlying films deformation after wire bond is studied by optical microscopy after removal of the pad Al, with additional measurements by FIB. Pad designs in this study are rated for robustness to cracking according to an optical “ripple effect” deformation scale. “Ripple” is so named because it has a similar appearance to water ripples. It is due to non-uniform deformation in the underlying Al film(s) in the pad structure. Though the Al material is fully constrained within the SiO2 dielectric body, it is able to migrate plastically into local “hills and valleys” during bonding stress, with the top dielectric film bending in conformance. Cracks can then initiate in the undulating upper dielectric when its tensile strength is exceeded. “Ripple” in these pads is seen to vary depending upon the underlying metallization pattern and density as well as with wire bonding stress, for a fixed pad Al thickness. Traditional-style Al metallization pad structures with full metal plates are least robust, being the most prone to high “ripple” and cracks. Other pad structures more indicative of BOAC designs show varying degrees of improved robustness to cracking as shown by decreasing “ripple”. Results show that significant improvements in pad robustness to cracking are feasible in BOAC designs which include top-metal-minus-one routing in Al-metallization technologies, while providing increased process margin in wire bond, permitting efficient use of die area without extra processing or new issues.

A switched-capacitor PWM generator for LCD backlight brightness control

In this paper, a pulse width modulation (PWM) generator based on a switched capacitor for LCD backlight brightness control is described. The proposed scheme uses a simple RC network along with a clocked-comparator which samples the output of the ambient light sensor, and generates a PWM signal corresponding to the light level. Furthermore, by using a switched-capacitor resistor with variable clock frequency, the RC time constant is programmable and less sensitive to process variations with respect to passive resistors. In addition, it is shown that the linearity of the proposed PWM generator can be enhanced by replacing the RC network resistor with a constant current source. The operation of the PWM generator is verified through circuit level simulations, and the prototype circuit is fabricated using CMOS 0.18um technology.

WCVD Seam Hole Improvement to Prevent BEOL Copper Diffusion

With the feature size shrinking in IC manufacturing, copper is to be used in BEOL metallization to decrease RC delay and improve electro-migration for 0.13um technology node and below. Moreover, tungsten still remains as the material of choice for the contact. As reported in most papers, copper is easily to diffuse through the seam of tungsten plug. Many researches focus on the dielectrics or Ta/TaN barrier layer enhancement to prevent Cu diffusion. In our study, another copper diffusion mechanism, which tunnels through the contact Tungsten seam hole and induces product device failure, is proposed. WCVD process optimization for seam hole improvement is also studied to prevent copper diffusion.

Radiation Tolerance of NROM Embedded Products

Radiation tolerance of NROM memories is demonstrated at the level of industrial 4 Mbit memory embedded modules, specifically not designed for operation in radiation harsh environments. The memory fabricated in 0.18 um technology remains fully functional after total ionization doses exceeding 100 krad. The tests were performed by irradiating with <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\gamma$</tex></formula> -rays ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$^{60}{\rm Co}$</tex></formula> source) and 10 MeV <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{11}{\rm B}$</tex></formula> ions in active (during programming/erase and read-out) and passive (no bias) modes. Comprehensive statistics were obtained by using large memory arrays and comparison of the data with the parameters of irradiated single cells allowed deep understanding of the physical phenomena in the irradiated NROM devices for both moderate ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$&lt;$</tex></formula> 1 Mrad) and large ( <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$&gt;$</tex> </formula> 1 Mrad) TID. The obtained data is currently employed in the design of the new generation of NROM memories, having improved radiation tolerance

Design of a Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.

Design of A Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.

A Study on PVD Co Pre-clean Chamber RF Reflect Power Improvement

For 0.18um and 0.13 um technology, Co/TiN deposition process is widely used to form CoSix to provide the needed lower contact resistance of the polysilicon gate. CoSix formation is sensitive to pre-existing wafer surface native oxides and ambient contamination. Pre-clean process before Co film deposition is required to remove residues before Co/TiN deposition. The corresponding chamber RF reflected power too high issue during this pre-clean has significant impact on the etch rate and particle performance. In this paper, three approaches to reduce Co pre-clean chamber RF reflect power are presented.

Via Resistance Variation Improvement Through Amine Versus Fluorine Based Chemical and O2 Dry Flushing for BiCMOS Technology

The paper discussed the via resistance variation using different cleaning chemicals known as the amine and fluorine based chemical for 0.6um BiCMOS technology. Single and chain via resistance showed severe drift with fluorine based clean recipe especially at the wafer edge where the failure rate is approximately 28% for chain via resistance and 12% for single via resistance. The baseline chemical, amine based showed low failure rate of less than 3%. Resistance drift is mainly due to the high Ti/TiN polymer residues which are remained at the bottom of the via holes. This is because 0.6um technology tend to generate more by-products since the etch amount is higher compared to other advanced technology which have smaller critical dimension (CD) size. Focus of the paper is mainly on the recipe optimization with fluorine based chemical where the objective is to have comparable via resistance performance with the amine based chemical. Recipe was optimized for different wet cleaning tool, which includes Batch Spray Type and Single Wafer Type. All optimise recipes showed comparable via resistance performance with the amine based chemical. Apart from that, a study on via resistance by adding O2 flushing etch step was conducted. The study was conducted on dual plasma source chamber and single plasma source chamber for BiCMOS technology. Adding O2 flushing step helps to scavenge some of the polymer on the wafer. Single plasma source chamber with O2 flushing step has better performance on production recipe compared to dual plasma source chamber.

Macroblock Feature Based Adaptive Propagate Partial SAD Architecture for HDTV Application

A macroblock (MB) feature based adaptive propagate partial SAD architecture is proposed in this paper. Firstly, by using edge detection operator, the homogeneous MB is detected before motion estimation and three hardware friendly subsampling patterns are adaptively selected for MB with different homogeneity. The proposed architecture uses four different processing elements to realize adaptive subsampling scheme. Secondly, in order to achieve data reuse and power reduction in memory part, the reference pixels in search window are reorganization into two memory groups, which output pixel data interactively for adaptive subsampling. Moreover, a compressor tree based circuit level optimization is included in our design to reduce hardware cost. Synthesized with TSMC 0.18um technology, averagely 10k gates hardware can be reduced for the whole IME engine based on our optimization. With 481k gates at 110.5MHz, an 720-p, 30-fps HDTV integer motion estimation engine is designed. Compared with previous work, our design can achieve 39.8% reduction in power consumption with only 3.44% increase in hardware.

A low-power baseband modem architecture for a mobile RFID reader

Currently the RFID (Radio Frequency IDentification) systems become used in many areas, especially for delivery, manufacturing, and maintenance of goods. For example, a tag reader or a tag interrogator communicates with tags attached on goods, reads their identification codes, and accesses their related database through a network infrastructure. This approach makes it easy to maintain goods very efficiently in large-scale markets, delivery systems, and so on. There are many research activities in RFID systems for industrial applications, but there is few on mobile and portable devices such as cellular phones and PDAs. This paper presents an architecture overview of a multi-protocol RFID reader on mobile devices with detailed description of hardware implementation. We have considered several design parameters, such as low power consumption, cost effectiveness and flexibility. Also, since our architecture supports WIPI (Wireless Internet Platform for Interoperability), any WIPI application can use our RFID reader's functionalities to query tags' information from Internet through HAL interfaces. We prototyped our system on the ARM-based Excalibur FPGA with iPAQ PDA, and also a chip with 0.18~um technology for verification of our architecture.

A Highly Parallel Joint VLSI Architecture for Transforms in H.264/AVC

In H.264/AVC, the concept of adapting the transform size to the block size of motion-compensated prediction residue has proven to be an important coding tool. This paper presents highly parallel joint circuit architecture for 8?×?8 and 4?×?4 adaptive block-size transforms in H.264/AVC. By decomposing the 8?×?8 transform to basic 4?×?4 transforms, a unified architecture is designed for both 8?×?8 and 4?×?4 transform and the transform data-path can be efficiently reused for six kinds of transforms. i.e., 8?×?8 forward, 8?×?8 inverse, 4?×?4 forward, 4?×?4 inverse, forward-Hadamard, inverse-Hadamard transforms. Linear shift mapping is applied on the memory buffer to support parallel access both in row and column directions which eliminates the need for a transpose circuit. For reusable and configurable transform data-path, a multiple-stage pipeline is designed to reduce the critical path length and increase throughput. The design is implemented under UMC 0.18 um technology at 200 MHz with 13.651 K logic gates, which can support 1,920?×?1,088 30 fps H.264/AVC HDTV decoder.

Control and Observation Structure for Analog Circuits with Current Test Data

This work presents a current-mode control and observation structure (CMCOS) for analog circuits with current test data. Current store cells (CSCs) are used in the proposed CMCOS to enhance the controllability and observability. The proposed CMCOS can be used to observe several test points, which can be simultaneously sampled and controlled using current test data. Additionally, the proposed CMCOS enables designers to use one channel of an oscilloscope to monitor simultaneously several output waveforms of analog circuits or systems. The physical chip of a two-stage CMCOS was fabricated using TSMC 1P4M CMOS 0.35 um technology. Also, experiments were performed to confirm the theoretical analysis.

Scaling and Integration of High Performance Interconnects

ABSTRACTInterconnect delay is believed to have a dominating impact on the speed of large logic circuits (such as micro-processors) when the Si technology is scaled into sub- 0.25um generations. In this paper, we analyzed interconnect scaling issues based on leading micro-processor trend data, simple RC delay model and the “Rents' rule”. It was concluded that, in order to not limit the speed of large logic circuits, “fat” metal wires need to be used for upper metal layers, which will lead to a rapid increase of required number of metal layers (&gt;10) for sub-0.25um technology generations. Introducing Cu and low ε interconnect system can delay this rapid increase by ∼1 generation. Creating multiple clock frequencies in large logic chips and reducing the size of high frequency islands appears effective in containing the interconnection delay problem. Therefore, the proposed interconnection scaling/development strategy is to introduce Cu and low ε dielectric into manufacturing in next 1∼3 generation (0.25um∼0.13um), develop low cost and high yield interconnect system to enable ∼10 interconnect layers, and improve circuit design methodology to reduce high frequency island size.