Abstract
The computation of JND is very complex, which makes it difficult to embed it into integrated circuits. To solve this problem, Haar-DWT based JND model is exploited and its corresponding pipeline architecture is developed in this paper. To evaluate its performance, the architecture is modeled with hardware description language, and implemented by SMIC 0.18um technology. The area of JND core is 42052 gates, which is significantly smaller than the full band JND based architecture. From the experiment results, the system goes on well at 161 MHz and achieves 78% time saving compared with the full band JND based architecture.
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