Efficient pipelined VLSI architectre with dual scanning method for 2-D lifting-based Discrete Wavelet Transform

Abstract

In this paper, we describe a high speed, memory efficient, very low power and dual memory scan based pipelined VLSI architecture for 2-D Discrete Wavelet Transform (DWT) based on Legall 5/3 filter. Proposed architecture consists of two 1-D pipelined architectures along with transpose unit (TU). Architecture consumes two inputs per clock cycle and produces two outputs per cycle. Moreover dual scan technique is employ to enhance throughput with 100% hardware utilization efficiency without significant increase in power. This architecture uses 2N on chip buffer and five transpose register to process single level 2-D DWT of image size of N×N. RTL (Register Transfer Level) is written using VHDL and netlist is compiled using Synopsys Design Vision using UMC 180 nm MMRF technology cell library. After formal verification netlist is imported to cadence Soc encounter for GDS-II file generation for (Application Specific Integrated Circuit) ASIC. Simulation results show positive slack with 200 Mhz frequency. Core area of proposed architecture is only 0.73 mm2 with low power consumption such as 13.38 mw.