Um Technology Research Articles

Design of Low Power and Process Control Hybrid Adder with Complemented Carry Structure

A Hybrid logic style is most popular when compared to other logic styles in implementation of full adder circuits. Conventional hybrid adder uses truth table with true form of carry in and carry out. This will result in non-identical outputs of sum and carry for about 75% of the input combinations. Alternate truth table has been proposed to increase the similarity of sum and carry outputs. In this paper, circuit is designed for complemented carry in and complemented carry out of full adder. This novel structure allowed to design 20-T hybrid adder with process control, low power and low power delay product. The proposed adder structure is applicable for ripple carry adder. The performance of the designs is measured by simulating it in tanner T-spice environment using 0.25um technology. Proposed design has also been implemented up to 64-bit for its scalability. All the results were taken at several operating frequencies with varying word size of the adder. The proposed adder minimizes the power by 9.5%-51.5% and the power delay product by 3%-60% when compared to its counterparts for N-bit adder.

Topologies of Complementary Metal Oxide Semiconductor Transimpedance Amplifier

In this paper, a similar investigation of various CMOS amplifier has been introduced. Standard gadget boundaries of transimpedance enhancer like input referred noise, power dissipation is considered and thought about. Here, the transimpedance amplifier is partitioned based on its geography and gadget innovation utilized, also execution is summed up to get the outline. The greater part of the investigation taken are performed on 0.18um technology.

An Ultra-low Power Off Chip Capacitor-less LDO With High Transient Response

This paper presents a low-dropout linear regulator (LDO) with ultra-low power high transient response. This LDO adopts GAP-dynamic-bias circuit to achieve quiescent current as low as 242nA under 0-20mA load. A transient enhancement circuit based on window comparator is used to sense the output voltage change and further enhance the transient response. The circuit is designed and implemented using TSMC0.18um technology, and is verified by simulation using Spectre software. The simulation results show that when the load changes in the range of 10uA-20mA with a 1ns transition edge, the slowest overshoot and undershoot recovery times are only 2.36us and 2.15us. In the input voltage range of 2.5-3.6V, the linear regulation rate and load regulation rate are 0.479mV/V and 2.61nv/mA, respectively.

A Novel Undistorted Image Fusion and DWT Based Compression Model with FPGA Implementation for Medical Applications

The usage of a fused image and compressed model in a VLSI implementation is demonstrated. In this study, distortion correction is also considered. In distortion correction models, least-squares estimate is utilized. The technique of picture fusion is widely employed in medical imaging. Many pictures are obtained from various sensors (or) multiple images are captured at different times by one sensor in the image fusion approach. CT scans give useful information on denser tissue with the least amount of distortion. The information obtained from a magnetic resonance imaging (MRI) of soft tissue with significant distortion is useful. The DWT-based image fusion approach employs discrete wavelet transforms, a novel multi-resolution analytic tool. Back mapping expansion polynomial is used to reduce computer complexity. Using 0.18um technology, the suggested VLSI design achieves 218MHz with 1480 logical components.

A Novel Approach for Low Phase Noise Voltage Controlled Oscillator Design based on TSMC 0.18 um Technology

In this paper, a new structure of Voltage Control Oscillator (VCO) to reduce the phase noise using two plans of a variable voltage capacitor is proposed. The aim of the current paper is to analyse two structure of a completely integrated 3.7 GHz LC-VCO based on TSMC 0.18 um technology. In the first plan for different voltages with variable voltage capacitors in this circuit can be achieved to a suitable phase noise of about 125 dB per Hz and in the second plan, a noise of -123 dB per Hz is achieved in the deviation frequency of 1 MHz. Also, the Figure of Merit (FOM) values for the first plan of -4/186 and for the second plan of –4/184 are achieved and the power consumption is 10 mW.

A NOVEL PARALLEL 4X4 TRANSFORM AND INVERSE TRANSFORM ARCHITECTURE FOR H.264

The H.264 video coding standard provides a compression gain of 1.5 x 2.0 x over H.263 and MPEG- simple profile. One of the major differences between H.263 and H.264 is the transform coding. The transforms of H.264 employ only integer arithmetic operations such as additions and shifts without multiplications, with coefficients and scaling factors that allow for 16-bit arithmetic computation on first-level transforms. The integer transforms also solve the mismatch problem like H.263. These changes lead to a significant complexity reduction, but with only less than 0.02 dB decrease in PSNR. A novel parallel 4x4 multiple transforms architecture for H.264 is presented in this paper. This architecture is based on Wallace trees and can process 4 inputs in parallel. This architecture has been designed and synthesized in SMIC 0.18um technology. The result shows that this architecture can achieves above 1,200M pixels/sec throughout and consume only 5625 gates. The timing-area property of this architecture is improved compared with the previous architecture.

A new design strategy for bandwidth and efficiency enhancement in KA band CMOS power amplifier

PurposeThe purpose of this paper is to propose a new design strategy to enhance the bandwidth and efficiency of the power amplifier.Design/methodology/approachTo realize the introduced design strategy, a power amplifier was designed using TSMC CMOS 0.18um technology for operating in the Ka-band, i.e. the frequency range of 26.5-40 GHz. To design the power amplifier, first, a power divider (PD) with a very wide bandwidth, i.e. 1-40 GHz, was designed to cover the whole Ka-band. The designed Doherty power amplifier consisted of two different amplification paths called main and auxiliary. To amplify the signal in each of the two pathways, a cascade distributed power amplifier was used. The main reason for combining the distributed structure and cascade structure was to increase the gain and linearity of the power amplifier.FindingsMeasurements results for designed power dividers are in good agreement with simulations results. The simulation results for the introduced structure of the power amplifier indicated that the gain of the proposed power amplifier at the frequency of 26-35 GHz was more than 30 dB. The diagram of return loss at the input and output of the power amplifier in the whole Ka-band was less than −8dB. The maximum power-added efficiency (PAE) of the designed power amplifier was 80%. The output P1dB of the introduced structure was 36 dB and the output power of the power amplifier was 36 dBm. Finally, the IP3 value of the power amplifier was about 17 dB.Originality/valueThe strategy presented in this paper is based on the usage of Doherty and distributed structures and a new wideband power divider to benefit from their advantages simultaneously.

13.3: A new pixel structure for OLEDoS micro‐display

In this paper, we propose a new pixel structure for the organic Light Emitting Diode (OLED) 0.65 inch SVGA resolution micro‐display with 8 bit gray level. The proposed pixel structure is composed of 4 MOSFETS and one capacitor to integrate the pixel structure in the restricted pixel area (9um×9um) using 0.18um technology. The simulation result shows that the maximum error of emission current occurs at high gray level.

Error Detection of Data Conversion in Flash ADC using Code Width Based Technique

Abstract The high integration density of the complex electronic system requires the multi-functional testing facility to ensure the accuracy of the circuit function. In addition, the wide population of submicron technologies results in the persistent requirements of high precision analog and mixed-signal (AMS) circuits. In the complex, high-density circuits, observing the correctness of output are limited due to the limitations of input and output pins which develop the AMS circuit test as very difficult and expensive. A digital built-in self-test (BIST) scheme has been presented in this paper for testing an analog to digital converter (ADC) in the time domain. The testing scheme consists of the linear analog ramp generator, ADC as a circuit under test, output response analyzer and a BIST controller. Bootstrap linear ramp generator is used to generate the linear analog ramp signal which is applied to ADC to develop the digital word sequence for testing. Among various types of ADCs, here a Flash ADC has used since it is fastest and accurate in digital conversion. A Flash ADC has been designed with the seven-bit resolution and tested using the proposed digital BIST scheme. The ADC comprises a sample-hold circuit, 2N -1 comparator, XOR gates, and encoder block. The output response analyzer verifies the digital output sequence to validate the static test parameters of ADC called monotonicity, missing codes, DNL, and INL error. The BIST controller generates the control signals to control the test sequence. The complete test sequence of ADC BIST has simulated in Tanner EDA with TSMC 0.18um technology. ORA is used to analyze the presence of monotonicity, missing codes, DNL and INL error in the ADC output.

A High Throughput JPEG2000 Entropy Decoding Unit Architecture

This paper is dedicated to a hardware architecture development for JPEG2000 entropy decoding unit (EDU) which consist of two parts: context modeling unit (CMU) and arithmetic decoding unit (ADU). To achieve a high throughput we propose an efficient pixel skipping scheme to save clock cycles for non-context position in CMU and realize the ADU logic by combinational circuit to keep the result of ADU within the same clock of context which can reduce the latency to zero clock cycle between CMU and ADU. We show that the proposed EDU architecture attains a throughput of 68.66–232.14 Mbps for a single decoding core depending on compression ratios, and consumes 95.79 mW based on SMIC 0.13 um technology. In comparison with the state-of-the-art decoders the proposed EDU architecture provides consistent reconstruction performance with software decoder and comparable throughput, memory and power consumption.

Partial reset HDR image sensor with improved fixed pattern noise performance

An efficient method is presented to achieve 4T pixel dynamic range extension whilst keeping the fixed pattern noise (FPN) low. The method utilizes the floating diffusion node as a secondary photocharge integration node with a partial reset applied to the floating diffusion node. The output image signal is a recombination of the linear signal integrated in the photodiode node, and a compressed signal integrated in the floating diffusion node. The recombination algorithm suppresses the FPN stemming from the variable transfer gate potential barrier height. An image sensor array of 1344x1008 pixels was built in 0.11um technology. We demonstrate the preservation of low light sensitivity of 4T pixels, a dark noise of 3.5e-, and a dynamic range for the current sensor of 115 dB, with potential to greatly exceed 120-dB. Further, the FPN stemming from the transfer gate potential barrier height variation does not degrade the image; the pixel compressive response can be controlled on a per frame basis depending on the scene, and the HDR scene is captured during one frame. The sensor combines the properties that are crucial for automotive and other machine vision applications.

The BLIXER, Integrated Balun-LNA-Mixer for ZigBee Application

Objectives: The main objective of this paper is to design a Blixer using noise-cancelling technique and balun –LNA-Mixer for better performance. Methods: As studied in literature of mixers, it shows they have less bandwidth disadvantage. This paper is concentrated to realize a wide bandwidth mixer by keeping the real part of the impedance of all RF nodes low, and using this mixer there is no capacitive loading problem. Findings: By avoiding use of inductors, the on chip size of circuit will be reduced and also the bandwidth extension requirement is fulfilled. This gives less DC-voltage drop after IF filtering. The design is implemented and simulated using Advanced Design System tool in CMOS 0.18um technology. The noise figure of the final BLIXER is obtained as 0.6dB and that of LNA is less than 2dB. This results are one of the best seen for a BLIXER. Applications: This design is well suited for wideband ZigBee receiver in wireless communication systems.

차량용 LIN 제어기의 설계 및 검증

차량 내 전자장치에서 효과적인 서브 버스로서 표준화된 저속 직렬 통신 프로토콜인 LIN(local interconnect network)이 개발되었다. 본 논문에서는 LIN 버전 2.2A를 기반으로 LIN 제어기를 Verilog HDL을 이용하여 구현하였다. 구현된 LIN 제어기는 FPGA에서 동작을 확인하였으며 IP 형태로 제공되어 SoC 시스템에 통합이 가능하다. 0.18um 공정에서 합성하였을 때의 게이트 수는 약 2,300 게이트이다. LIN (local interconnect network) is a standard low-speed serial communication protocol, and it was developed as an efficient sub-bus for automotive electronic modules. In this paper, a LIN controller was implemented in Verilog HDL, based on LIN ver. 2.2A. The implemented LIN controller was verified in FPGA, and it can be supplied as an IP to be integrated into SoC system. Its size is about 2,300 gates when synthesized in 0.18um technology.

Dual-parameter control of the pole frequency in case of universal filter with MCDU elements

This paper presents an universal filter with control of the pole frequency by two mutually independent parameters--current gain (B) and intrinsic resistance (Rx) in frame of two modified current differencing unit (MCDU) active elements. This type of control extends and also improves features of the tuning range and is referred to as dual-parameter control. The current-mode filter is of the second order and the required type of the response (low pass, inverting band pass, high pass, band reject and all pass) is obtained by proper selection/combination of input(s)--this filter is of the multiple-input single-output type. The filter employs two capacitors, two MCDUs, each of them with four controllable parameters and one multiple-output current follower. The paper includes tuning range analysis, the simulation results with behavioral models and also laboratory measurement results with the same models. Moreover, designed transistor-level structures of both the active elements proposed in ON Semiconductor I3T CMOS 0.35 um technology that were used for final simulations confirm the workability and features of the designed concept.

A low noise preamplifier for silicon drift detectors

The paper describes a preamplifier, elaborated to process the signals of silicon X-ray drift detectors. The preamplifier has been designed in CMOS 0.35 um technology and optimized for operation with detectors, having capacitances of 100 fF. The feedback capacitance of 10 fF provides a gain of 100 mV/fC, ENC at T = −30°C equals 4 e (simulation result) at using shaper of the 6th order with a time constant of 8 us. Power consumption is 1.3 mW (preamplifier and shaper).

고효율 5A용 동기식 DC-DC Buck 컨버터

This paper presents high efficiency 5A synchronous DC-DC buck converter. The proposed DC-DC buck converter works from 4.5V to 18V input voltage range, and provides up to 5A of continuous output current and output voltage adjustable down to 0.8V. This chip is packaged MCP(multi-chip package) with control chip, top side P-CH switch, and bottom side N-CH switch. This chip is designed in a 25V high voltage CMOS 0.35um technology. It has a maximum power efficiency of up to 94% and internal 3msec soft start and fixed 500KHz PWM(Pulse Width Modulation) operations. It also includes cycle by cycle current limit function, short and thermal shutdown protection circuit at 150℃. This chip size is 2190um*1130um includes scribe lane 10um.

Design of Low Voltage and High-Speed BiCMOS Buffer for Driving Large Load Capacitor

BICMOS circuits are interesting for designers when a high speed output driver is required especially in I/O circuits. Buffer is an important block in high speed circuits, so designing a buffer with high drive capability has a great effect on circuits with large load capacitor. This paper presents a new BiCMOS buffer which uses 32nm technology node for CMOS transistors and 0.18um technology node for BJT transistors. The proposed buffer operates properly in voltage ranges from 0.8v to 1.5v. The capacitor range is from 0.5pf to 200pf; the overshoot of the output in this capacitor range is less than 10% of the supply voltage that is negligible. The proposed design has improvements in delay for about %88 respectively compared to similar CMOS buffers with high capacitor values.

우회 빈의 병렬처리가 가능한 HEVC CABAC 부호화기의 설계

HEVC CABAC에서는 하나의 빈을 부호화한 후 확률 모델을 업데이트하고, 업데이트된 확률 모델로 다음 빈을 부호화한다. 기존 CABAC 부호화기는 매 사이클마다 1개의 빈밖에는 부호화하지 못하여 처리율을 향상시킬 수 없었다. 본 논문에서는 확률 모델의 업데이트가 필요없는 우회 빈을 병렬처리 함으로서 처리율을 높인 HEVC CABAC 부호화기를 제안한다. 설계된 CABAC 부호화기는 매 사이클마다 1개의 정규 빈을 처리하거나 최대 4개의 우회 빈을 처리할 수 있으며, 평균적으로 매 사이클당 1.15~1.92개의 빈을 처리한다. 0.18 um 공정에서 합성한 결과, 게이트 수는 메모리를 포함하여 78,698 게이트, 최대 동작 속도는 136 MHz, 최대 처리율은 261 Mbin/s이다. In the HEVC CABAC, the probability model is updated after a bin is encoded and next bin is encoded based on the updated probability model. Conventional CABAC encoders can encode only one bin per cycle, which cannot increase the encoding throughput. The probability model does not need to be updated in the bypass bins. In this paper, a HEVC CABAC encoder is proposed to increase encoding throughput by parallel processing of bypass bins. The designed CABAC encoder can process either a regular bin or maximum 4 bypass bins in a cycle. On the average, it can process 1.15~1.92 bins in a cycle. Synthesized in 0.18 um technology, its gate count, maximum operating speed, and the maximum throughput are 78,698 gates, 136 MHz, and 261 Mbin/s, respectively.

데이터 전송을 위한 전용 명령어 및 I/O 포트를 탑재한 8051 마이크로콘트롤러의 설계

본 논문에서는 데이터 전송을 위한 전용 명령어 및 I/O 포트를 탑재한 8051 마이크로콘트롤러를 설계하였다. 설계된 8051마이크로콘트롤러는 외부 디바이스를 제어하고 데이터를 주고받기 위해 2개의 UART 포트와 1개의 SMBus 포트를 탑재하였으며, 이들 포트를 운용하기 위한 전용 명령어를 개발하여 명령어 집합에 추가하였다. 이에 따라 여러 디바이스를 동시에 제어하고 데이터를 전송할 수 있으며, 응용 프로그램의 코드 크기도 줄일 수 있다. 특히, 다수의 디바이스와 데이터를 주고받는 동안에도 마이크로콘트롤러가 멈추지 않고 다른 프로그램을 수행할 수 있어서 동작 효율을 크게 향상할 수 있다. 0.18 um 공정에서 합성한 결과, 전용 명령어 추가로 인한 하드웨어 크기 증가는 무시할만하며, 모든 명령어 및 I/O 포트가 정상적으로 동작하는 것을 FPGA 보드에서 확인하였다. In this paper, an 8051 microcontroller with application-specific instructions and I/O ports for data transmission is designed. The designed microcontoller includes two UART ports and one SMBus port to control external devices and to transmit data with them. Application-specific instruction is developed and added to the instruction set to exploit these I/O ports. So the designed microcontroller can perform multi-device control and multi-byte transmission. Also, it can reduce the code size of the application program. Especially, the designed microcontroller does not stall and can execute other programs during data transmission, which significantly increases its efficiency. Synthesized in 0.18 um technology, the area overhead due to application-specific instructions was negligible. Operations of all instructions and I/O ports were verified to run correctly on a FPGA board.

HEVC 및 VP9 겸용 통합 역변환기의 설계

In this paper, a unified inverse transformer is designed for HEVC and VP9. The proposed architecture performs all modes of HEVC and VP9 in the unified inverser transformer, such as HEVC IDCT, HEVC IDST, VP9 IDCT, VP9 IADST and IWHT. Same computations are used in HEVC IDCT and VP9 IDCT, except for the scales of the coefficients. Similarly, same computations are used in HEVC IDST and VP9 IADST, except for the scales of the coefficients. Furthermore, HEVC IDCT, VP9 IDCT, and VP9 IADST are the subsets of upper level IDCTs. The proposed architecture reuses multipliers when the computation is identical. Also it shares adders and butterfly structures even when the multiplier coefficients are different. So it reduces the hardware size significantly. Synthesized in 0.18 um technology, the gate count is 456,442 gates. which achieved 22.6% reduction compared to conventional architectures.