Ultra Low-k Materials Research Articles

(Invited) Barrier Slurry Innovation for Cu-ULK Process

With the application of Ultra low-k dielectric material in the advanced nodes, more and more challenges are elevated on barrier CMP. High removal rates of TEOS and barrier films are required to enable an effective removal, while tunable Cu RR and low ULK RR are needed to control the topography and stop in ULK layer. The k value shift of polished ULK also should be minimized. In this paper, we will report a barrier slurry for this application including slurry additives effect on removal rate selectivity, topography and k value. The corrosion control capability is also evaluated by soaking test. Through slurry formulation tuning, an optimal topography with good within wafer and within die non-uniformity are obtained. The control capability in removal rate and selectivity, k value shift of polished ULK, topography, and Cu corrosion were demonstrated.

The Optimization of Metal Hard-Mask Based All-in-One Etch

Metal hard-mask based all-in-one etch scheme has been extensively integrated with Cu interconnects for its significant improvement in terms of the line sidewall roughness, the reduction of ultra low-k material damage and the enhancement of lithography process window. In this paper, we investigated the trade-off relationship between electromigration (EM) and time-dependence break-down (TDDB) on one AMEC (Advanced Micro-fabrication Equipment Company) test vehicle. This etcher features the special switchable rf-power at bottom electrode. Results indicate the dynamic ESC (electrostatic chuck) is imperative to meet the quite different temperature demands between via etch and trench etch step, thus reducing the via encroachment on metal hard-mask while no metallic residue is detected at trench bottom. Meanwhile, the tunable edge ring coupled with the optimization of trench etch gases are also critical to deliver the on-target Rc and reliability performance. In brief, we successfully demonstrated the partial SAV (self-aligned via) could deliver the on-target WAT and reliability performance on AD-RIE.

Design of lamellar structured POSS/BPZ polybenzoxazine nanocomposites as a novel class of ultra low-k dielectric materials

A novel class of lamellar structured polyhedral oligomeric silsesquioxane/bisphenol Z (POSS/BPZ) polybenzoxazine (PBz) nanocomposites was successfully designed by a facile one-step copolymerization technique.

A multilevel sub-modeling approach to evaluate 3D IC packaging induced stress on hybrid interconnect structures

As the technology node progress, interconnect structures continue to evolve with decreasing dimensions and increasing number of layers and complexity. Besides, low-k or ultra-low-k (ULK) dielectric materials are required to decrease the RC delay in the interconnect and improve performance. The main disadvantages of ULK material are the weak mechanical properties and poor adhesion which makes the stacking and packing process for 3D IC’s a big challenge. The impact of Chip Package Interaction on a 7 layer interconnect structure with different combinations of hybrid low-k dielectric is studied using multilevel sub-modeling technique. It was found two main mechanisms inducing stress: (a) global, where the stress is caused by the overall package deformation and (b) local mechanism, where the constant of thermal expansion (CTE) mismatch between Cu interconnect and low-k is the main cause for stress. The results showed that interconnect structure fully integrate in soft dielectric material positioned at the edge of μbump present more risk of failure due to high tensile stress introduced by the global package deformation. For hybrid interconnect structures, local tensile stress due to CTE mismatch between Cu line and its surrounded material is the main cause of failure, regardless the position on the die.

Influence of porosity on dielectric breakdown of ultralow-k dielectrics

The effect of porosity on the electrical properties of porogen-free ultralow-k dielectric materials was demonstrated using a special curing process that allows a separate control of porosity and matrix properties. It is shown that the leakage current was insensitive to porosity, suggesting a bulk conduction mechanism. On the other hand, higher porosity leads to lower breakdown voltage, indicating that porosity can degrade the electrical reliability performance of the dielectric material. The observed lower breakdown field is explained in terms of the amount of cage structure in the film, the exacerbation of strain in the Si–O–Si backbone structure by an external electric field, and local field enhancements near the pores, thereby making the Si–O bond highly susceptible to breakage.

Ultra Low-k Damage Control and k Recovery for 28nm RC Improvement

To improve resistance-capacitance delay, porous ultra low-k dielectric materials are used in advanced copper damascene integration. However, the BEOL processes often lead to low-k film damage by removing the hydrophobic groups Si-CH3, and convert partially low-k materials surface from hydrophobic to hydrophilic one. During the wet related processes, the hydrophilic porous low-k film surface is easy to absorb moisture and potentially increase k-value. In this work, we developed the processes that can maintain ultra low-k film k-value either by repairing low-k damage or by removing moistrue. Dry etch plasma process is one of the main steps to result in low-k film damage. Post etch treatment (PET) was optimized to repair porous low-k film surface due to the etch damage. This improved process with less low-k damage can significantly reduced the moisture absorption in the following wet process and improve the capacitance by about 10%. Various thermal treatments post wet and post CMP processes were studied, including temperature, gases and pressures. From our results, post wet clean heat treatment can improve capacitance by about 5% and post CMP heat treatment can improve capacitance by about 10%. To decrease moisture absorption from atmosphere after the wafers were processed thru CMP, queue time from CMP to NDC deposition also was studied and the safe specification was also defined.

Adhesion analysis for on-chip interconnect structures by beam bending techniques with optical crack length determination

Crack propagation in BEoL (back-end of line) interconnect structures is a concern in terms of chip reliability. Due to the application of porous ultra low-k (ULK) materials, a careful trade-off is necessary between reducing signal delays and also decreasing mechanical properties of the interconnect structures. Therefore, fast and reliable measurement techniques for characterizing mechanical properties as film adhesion and fracture toughness are needed. In the present investigation, a camera assisted double-cantilever beam (DCB) technique has been used to obtain locally resolved adhesion measurements within the die. Two chip designs, produced in leading-edge technology nodes with two different ULK materials, were tested. The Gc values measured within the die show a correlation to density and arrangement of the Cu structures. ULK containing metallization levels with lowest k values have been identified as preferred crack paths. The measurements are compared with results of the four-point bending (4PB) test not having the local resolution of DCB but typically used for unpatterned film stacks and possessing a mode I/II load mixity. The DCB tests yield reduced Gc values compared to the 4PB tests, which can be understood as result of the different loading modes of both techniques.

Effects of VUV and EUV Radiation on Ultra Low-k Materials Damage

ABSTRACTLow-k dielectric films can be substantially damaged during plasma processing. High energy UV and VUV photons emitted by plasma play the key role in damaging the porous low-k films directly or indirectly by stimulating chemical reactions with radicals in plasma and plasma afterglow. The different ULK samples (k: 2.0-2.2, porosity: 30-50%, pore radius: 1-2 nm) were studied by exposing to five radiation sources at various wavelengths (VUV: 193 nm, 147 nm, 104-106 nm, 58.3 nm, and EUV: 13.5 nm). Time-spatial behavior of the ULK damage as a function of photons fluence was studied by FTIR spectroscopy and XRF analysis. It is shown that the degree of damage depends on wavelength of UV light. The major UV damage was observed at the wavelengths below 193 nm. The maximum damage corresponds to 147 nm while the degree of damage at 58.3 nm was much smaller. In the case of organosilicate (OSG) based ULK materials, the degree of damage, as a rule, increases with porosity. Organic low-k materials are damaged more than OSG at 193 nm, but at shorter wavelengths (147, 106, 58.3 and 13.5 nm) they are more stable than OSG. One-dimensional model for radiation absorption and dynamics of CH3 group destruction in ULK films was developed. The cross-sections of photons absorption and photo-stimulated Si-CH3 bond breaking in ULK films for 13.5 -147 nm wavelength range were derived from a combined experimental and modeling study. The obtained values allow to simulate the VUV/EUV induced modifications of low-k materials with different composition, to understand better the mechanisms of plasma damage and to generate ideas for controllable modifications of low-k materials.

Unique Size-Dependent Challenges for BEOL Cleans in the Patterning of Sub-20 nm Features

BEOL Cleans has been and continues to be one of the most mysterious black boxes of semiconductor manufacturing. It has the unenviable task of removing post-plasma processing polymer residues, being compatible with ultra low-k dielectric materials that continue to scale k-value at the expense of material strength, and ensuring that any formulation that accomplishes the above objectives is also compatible with Cu and all other metals on the wafer used for liners or caps. In order to meet the performance requirements of next generation devices, Moore's law mandates continued scaling of dimensions with the additional challenges of size-dependent complexities for BEOL cleans development. Patterning of sub-20 nm features on thin ILD stacks suffers from the problems of etch-induced line undulation [1, 2] and cleans-induced pattern collapse [3]. High aspect ratio's, non-uniform drying, surface tension and low material strength have all been implicated as the root cause for pattern collapse during cleans [4]. Classical equations used to describe pattern collapse for resist lines that rely on 2D beam theory and finite element modeling [5] are not as applicable to patterned low-k dielectrics because material changes such as sidewall polymer residues, lowering of Young's modulus and changing pattern densities present different solid surfaces with widely varying wettability and diffusivity parameters [6, .

Time Dependent Dielectric Breakdown in Copper Low-k Interconnects: Mechanisms and Reliability Models

The time dependent dielectric breakdown phenomenon in copper low-k damascene interconnects for ultra large-scale integration is reviewed. The loss of insulation between neighboring interconnects represents an emerging back end-of-the-line reliability issue that is not fully understood. After describing the main dielectric leakage mechanisms in low-k materials (Poole-Frenkel and Schottky emission), the major dielectric reliability models that had appeared in the literature are discussed, namely: the Lloyd model, 1/E model, thermochemical E model, E1/2 models, E2 model and the Haase model. These models can be broadly categorized into those that consider only intrinsic breakdown (Lloyd, 1/E, E and Haase) and those that take into account copper migration in low-k materials (E1/2, E2). For each model, the physical assumptions and the proposed breakdown mechanism will be discussed, together with the quantitative relationship predicting the time to breakdown and supporting experimental data. Experimental attempts on validation of dielectric reliability models using data obtained from low field stressing are briefly discussed. The phenomenon of soft breakdown, which often precedes hard breakdown in porous ultra low-k materials, is highlighted for future research.

Impact of curing condition on chemical stability of ultralow-k PMO material.

ABSTRACTIn this work a new generation of periodic mesoporous organosilica (PMO) low-k dielectrics with targeted k-values 2.0 and 1.8 is evaluated. In addition, impact of two different curing processes on properties of the mesoporous material is analyzed. It is shown that removal of templating organics with thermal annealing leads to formation of mechanically robust and chemically very stable material, while application of UV-assisted curing with broadband lamp (λ > 200 nm) causes pronounced decrease of film ability to sustain in diluted HF solution. The explanation of that phenomenon is given in terms of silica-ring structures formed within organosilica skeleton.

Effect of catalyst HF concentration on the electrical characteristics of ultra low-k materials

The effects of catalyst HF concentration on the dielectric and electrical properties of SiOF films are discussed. From the current density-voltage and capacitance-voltage curves, we observed that the film catalyzed with the special concentration of HF (the ratio of HF/H2O = 1/5) shows good moisture resistance, low leakage current (10-11 A/cm2 at 1 MV/cm) and high breakdown field (6 MV/cm), which can be explained by the results of Fourier transform infrared spectra. The dielectric constant value is also very low and reaches about 1.75 after annealing at the temperature of 450?C. Therefore, the concentration of HF catalyst is an important factor in the sol-gel process.

Pore sealing of SiOCH ultra low-k dielectrics with polyimide Langmuir-Blodgett film

ABSTRACTContinuous decrease of the feature size of transistors in modern integrated circuits (ICs) constrains thickness of auxiliary dielectric layers in interconnects because of their relatively high dielectric constant, which reduces the efficiency of low-k material integration. Dielectric materials used today as barrier or etch-stop layers are usually SiN (k ∼ 7.0) and SiCN (k ∼ 4.8), which k-value significantly exceeds that of recent ultra low-k materials (k < 2.2). In our work we have investigated thin films of rigid-chain polyimide (PI) with a k-value of about 3.2-3.3. This film was deposited using a Langmuir-Blodgett (LB) technique and can be as thin as several monolayers. The intermolecular interaction of densely packed precursor macromolecules within a monolayer formed at the water-air interface makes it possible to avoid penetration of precursor material inside the pores. The latter peculiarity of the deposition process results in a pore sealing effect using a 4 nm PI film.

New generation of reactive pre-clean prior to barrier–seed deposition to preserve ULK integrity

Advanced interconnects development requires introduction of porous ultra low k (ULK) dielectrics enhancing product performance through parasitic capacitance reduction. ULK layers are characterized by higher carbon content and lower mechanical properties due to porosity increase. Consequently, ULK dielectrics are more prone to be damaged during plasma treatment in interconnects build [1]. Pre-clean processes prior to barrier/seed deposition are a potential area of concern for ULK integrity. Reactive pre-clean processes based on He/H2 plasma are investigated in this paper through two types of hardware. The new pre-clean chamber is an upgrade of conventional pre-clean hardware and combines optimized H2 plasma and active wafer temperature control to ensure efficient copper oxide reduction [3] and via cleaning. The aim of the paper is to evaluate performance of the new generation of reactive pre-clean compared to conventional hardware. To overcome ULK dielectric integration challenge, pre-clean processes need to ensure efficient copper oxide reduction and via bottom cleaning with minimum impact on ULK material properties. The ''new reactive pre-clean'' addresses these requirements for k=2.5 ULK materials. The new reactive pre-clean demonstrates a robust process window over a wide range of temperature and pressure settings for all characterized aspects. The ''new reactive pre-clean'' technology is seen to be a promising pre-clean candidate for next generation of porous ULK dielectric material ([email protected]?2.5) integration for 28nm node and beyond.

Influence of thermal cycles on the silylation process for recovering k-value and chemical structure of plasma damaged ultra-low-k materials

The integration of porous ultra low-k (ULK) materials within the interconnect system of integrated circuits is one of the most promising approaches to reduce RC-delay or crosstalk. The application of plasma processes for patterning, cleaning and photoresist removal is known to degrade the electrical parameters of the ULK by carbon depletion, densification and introduction of silanol species. In this study we investigate the influence of different thermally assisted immersion processes on the effectiveness of a silylation based k-restore process of plasma damaged porous low-k dielectrics. The results show that network recovery effects like methyl incorporation are different at the surface and in the depth of the damaged area addicted to precursor temperature and curing conditions. The most promising process sequence was shown to consist of an immersion at temperatures of 100-150^oC with subsequent UV anneal depending on the precursor used for recovery process.

Application of the Protection/Deprotection Strategy to the Science of Porous Materials

Selective protection of the porosity can be implemented in porous materials processing by using an organic polymer fill. This strategy is employed to protect ultralow-k (ULK) materials during patterning of 250-nm lines and spaces. Structures with significantly less sidewall and trench bottom damage are obtained, proving the potential of this novel approach in materials science.

Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond

Metrology and approaches necessary for selection of ultra low-k dielectric materials for future generation of IC devices are discussed. It is shown that porogen residue (sp2 hybridized carbon) formed during the UV curing of porogen based PECVD low-k materials increases the leakage current density and decreases the breakdown field. The amount of porogen residue increases with porosity because of larger amount of co-deposited porogen. Electrical characteristics of these films are significantly worse in comparison with low-k films prepared by using of self-assembling approaches without porogen. Therefore, utilization of porogen based technologies for preparation of ultra low-k films is limited. New metrologies allowing evaluation of intrinsic properties of low-k materials are discussed. It is shown that UV spectroscopy and a unique planar capacitor test vehicle are extremely important for evaluation of intrinsic properties of ultra low-k films.

Development of Porosimetry Techniques for the Characterization of Plasma-Treated Porous Ultra Low-k Materials

For the sub-32 nm node, porous SiCOH dielectrics (p-SiCOH) are integrated using dual damascene patterning by etching trenches and vias into the porous material. One challenge is to control the process conditions to minimize the plasma-induced damage of p-SiCOH materials at the bottom and at the sidewall of the trenches. Ellipsometric Porosimetry has been adapted to characterize the plasma-treated materials for both horizontal and vertical surfaces. Since surface modifications can cause adsorption and desorption delays and hydrophobicity loss, porosimetry measurements operated with multi-solvent and kinetic protocols are required. Quantitative measurements of vertically patterned materials are demonstrated using periodic structures of porous material and a Scatterometric Porosimetry analysis. Results show a good sensitivity of the measurement to the different process conditions but also highlight a different impact of the plasma processes on patterned materials compared with blanket films.

Development of Porosimetry Techniques for the Characterization of Plasma-Treated Porous Ultra Low-K Materials

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A Less Damaging Patterning Regime for a Successful Integration of Ultra Low-k Materials in Modern Nanoelectronic Devices

ABSTRACTThis paper describes a three-step process regime for the integration of porous SiCOH based ultra low-k materials in existing copper damascene technologies. During the work with these complex and sensitive materials, it became more and more clear, that a successful patterning depends not only on the etch step but also on the adjustment between the etch and the following cleaning and k-restore processes. The presented process regime starts with a reactive ion etch process for trench patterning followed by a post etch clean to remove etch residues. Finally a k-restore process was performed to repair the damaged regions in the trench sidewalls. In this work it became clear, that the etch chemistry influences not only the results of the etch process ostensibly sidewall damage but also kind and effect of the post etch clean. Each plasma composition results in the necessity of a customized post etch cleaning solution. Finally a k-restore process using Hexamethyldisilazane (HMDS) as restore chemical was demonstrated successfully. Enhanced temperatures and an additional UV-treatment are possibilities to promote the restore effect.