A multilevel sub-modeling approach to evaluate 3D IC packaging induced stress on hybrid interconnect structures

Abstract

As the technology node progress, interconnect structures continue to evolve with decreasing dimensions and increasing number of layers and complexity. Besides, low-k or ultra-low-k (ULK) dielectric materials are required to decrease the RC delay in the interconnect and improve performance. The main disadvantages of ULK material are the weak mechanical properties and poor adhesion which makes the stacking and packing process for 3D IC’s a big challenge. The impact of Chip Package Interaction on a 7 layer interconnect structure with different combinations of hybrid low-k dielectric is studied using multilevel sub-modeling technique. It was found two main mechanisms inducing stress: (a) global, where the stress is caused by the overall package deformation and (b) local mechanism, where the constant of thermal expansion (CTE) mismatch between Cu interconnect and low-k is the main cause for stress. The results showed that interconnect structure fully integrate in soft dielectric material positioned at the edge of μbump present more risk of failure due to high tensile stress introduced by the global package deformation. For hybrid interconnect structures, local tensile stress due to CTE mismatch between Cu line and its surrounded material is the main cause of failure, regardless the position on the die.