Die crack study for 40 nm lead free flip chip packaging

Abstract

Advanced wafer technology node has moved forward to 40 nm and below with an ultra low-K (ULK) dielectric constant value of 2.5. ULK shows lower mechanical strength and poor adhesion than that of low-K dielectric. Cu/ULK delamination becomes the major concern during the packaging reliability test. After eliminating the Cu/low-K delamination issue, experimental result shows that die crack become another major failure in 40 nm flip chip packaging reliability test after the temperature cycling test (TCT). The die crack failure can be detected by C-mode scanning acoustic microscopy (CSAM). CSAM image shows a crescent moon shape die crack. The scanning electron microscopy (SEM) cross-section image shows the crack was initialed from the underfill fillet upper part edge and penetrated to the die sidewall, then propagated toward to the active circuit side. Finite element simulation result shows that the die crack failure should initial from the die backside edge. The die crack was occurred by two mechanisms. The first is the bending stress at the die backside, which resulted by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. The second is the thermo-mechanical stress, which resulted by the local CTE mismatch between the silicon die and the underfill. Simulation parametric study shows that with low underfill fillet height and smaller fillet tip angle can reduce the thermo-mechanical stress. Besides, this work attaches a one-piece heat sink on the die to increase the packaging stiffness to resist the bending stress induced by the substrate shrinkage. This work verifies the two proposed solutions using the packaging TCT experiment. Experimental results demonstrate to lower the underfill fillet height, reduce the fillet tip angle or attach a heat sink on a flip-chip die are the effective way to solve the die crack issue.