Ultra Large Scale Integrated Circuits Research Articles

A newly developed Cu(Rh) alloy film and its characteristics and applications

A new type of copper (Cu)-rhodium (Rh)-alloy, Cu(Rh), films is developed by co-sputtering copper and rhodium onto silicon (Si) substrates under an argon (Ar) atmosphere. The new films are next annealed at 600 and 670 °C, or alternatively at 100 and 450 °C, for 1 h. Longer annealing to the films, for up to 8 days, is also conducted to explore resistivity variation. The resistivity of the new 300-nm-thick film is 2.19 μΩ cm after annealing at 670 °C for 1 h and drifts to 2.26 and 2.14 μΩ after annealing at 400 and 450 °C, respectively, for 200 h. A 2.7-μm-thick Sn layer is then thermally evaporated atop the new film for stable flip-chip solder joints; their metal and Cu-Sn intermetallic compound (IMC) growth processes vs. various annealing periods are tested. After annealing at 670 °C, the new 300-nm-thick film’s adhesive strength reaches 44.2 ± 0.01 MPa, which is 11 ~ 12-fold that of their pure Cu counterpart. Some key test results of the new film are disclosed herein, including its X-ray diffraction (XRD) patterns, transmission electron microscopy (TEM) images, secondary-ion mass spectrometry (SIMS), time-dependent dielectric-breakdown (TDDB) lifetime curves, and adhesive strength. The new film’s antibacterial efficacy arrives at an antibacterial ratio of approximately 100% against Staphylococcus aureus (S. aureus) BCRC 10451 for the 300-nm-thick film and approximately 99.82% for the 8 nm film, far superior to that of a pure Cu film, which is 0 with the same annealing temperature range. The new film, hence, seems to be a remarkable candidate material for various industrial applications, such as ultra-large-scale integrated circuits (ULSIC), micro-electronic circuits, printed circuits, flip-chip technology, medical care concerning antibacteria, and the like.Graphical A new type of copper (Cu)-rhodium (Rh)-alloy, Cu(Rh), films is developed by co-sputtering copper and rhodium onto silicon (Si) substrates under an argon (Ar) atmosphere and then annealing the new films at 600 and 670 °C, or alternatively at 100 and 450 °C, for 1 h. Longer annealing to the films, for up to 8 days, is also conducted to explore resistivity variation. The resistivity of the new 300-nm-thick film is 2.19 mW cm after annealing at 670°C for 1 h and drifts to 2.26 and 2.14 mW after annealing at 400 and 450 °C, respectively, for 200 h. A 2.7-μm-thick Sn layer is next thermally evaporated atop the new film for stable flip-chip solder joints; their metal and Cu-Sn intermetallic compound (IMC) growth processes vs. various annealing periods are tested. After annealing at 670°C, the new 300-nm-thick film’s adhesive strength reaches 44.2 ± 0.01 MPa, which is 11~12-fold that of their pure Cu counterpart. Some key test results of the new film are disclosed herein, including its X-ray diffraction (XRD) patterns, transmission electron microscopy (TEM) images, secondary-ion mass spectrometry (SIMS), time-dependent dielectric-breakdown (TDDB) lifetime curves, and adhesive strength. The new film’s antibacterial efficacy arrives at an antibacterial ratio of approximately 100% against Staphylococcus aureus (S. aureus) BCRC 10451 for the 300-nm-thick film and approximately 99.82% for the 8-nm film, far superior to that of a pure Cu film, which is 0 with the same annealing temperature range. The new film, hence, seems to be a remarkable candidate material for various industrial applications, such as ultra-large-scale integrated circuits (ULSIC), micro-electronic circuits, printed circuits, flip-chip technology, medical care concerning antibacteria, and the like.

Hyperdoped Crystalline Silicon for Infrared Photodetectors by Pulsed Laser Melting: A Review

Infrared photodetectors based on crystalline silicon have attracted much attention due to their low cost and good compatibility with complementary metal–oxide–semiconductor (CMOS) technology in ultra‐largescale integrated circuits (ULSI). However, silicon shows no response to infrared light with a wavelength of over 1100 nm corresponding to its bandgap of 1.12 eV. Pulsed laser melting and rapid solidification are effective ways to hyperdope high concentrations of deep‐level impurities into silicon, and therefore form an impurity band within the bandgap, allowing broad‐band infrared light to be absorbed. Herein, a review of the fundamentals and research progress of hyperdoped silicon and related infrared photodetectors during the past few decades is given. The fundamentals of hyperdoped silicon, including the hyperdoping mechanism and infrared light absorption or response, are first discussed. Then, the fabrication methodologies and properties of hyperdoped silicon with various elementals (chalcogens and transition metals) are illustrated, among which the corresponding photodetectors’ properties are stressed. Earlier research on chalcogen hyperdoping paves the path for silicon to be used for infrared photodetectors and later research on transition metals hyperdoping provides a new opportunity for further improvements of device properties. Finally, a summary and future research direction of hyperdoped silicon are outlined.

Dielectric contribution of the IR absorption bands of porous organosilicate glass thin films on a platinum sublayer

Reduction of interconnect capacitance is one of the key ways to increase the speed of an ultra-large-scale integrated circuit (ULSI). A porous organosilicate glass (OSG) thin film on a platinum sublayer was used as a test vehicle for modelling the conductor–insulator electrodynamic properties in an ULSI. Investigation of the structure and residual effect on the dielectric contributions of the IR absorption bands is a direct approach to control the dielectric properties of the film. The absorption band dispersion was simulated by the Drude–Lorentz equations within a framework consisting of a two-layer medium model. The contributions to the dielectric permittivity of IR absorption bands in thin OSG films with different volume porosities were determined. It was shown that the total dielectric permittivity in the IR region was approximately 10% lower than that at low frequencies of the order of 100 kHz. An additional contribution can arise as a result of low-energy excitations and H2O electrodipole relaxation in the microwave—THz range.

A surface potential model for tri-gate metal oxide semiconductor field effect transistor: Analysis below 10 nm channel length

In this study, an analytical model of Tri-gate metal-oxide-semiconductor field effect transistor (TGMOSFET) for short channel lengths below 10 nm is suggested and Technology computer-aided design (TCAD) simulation is used for confirmation. Two dimensional (2D) Poisson’s equation is solved with symmetric and asymmetric double gate (DG) MOSFET separately and is combined using the perimeter-weighted sum approach to model the surface potential of lightly doped silicon TGMOSFET. The model is examined by varying channel length, oxide thickness, gate voltage, drain voltage and doping concentration. In this study, the ratio of channel length to width is always kept greater than or equal to two. The structure is also inspected with a high-k dielectric material. A relative study of hafnium oxide (HfO2) and silicon dioxide (SiO2) with identical oxide thicknesses is given to explore the effect of high dielectric material on the model of TGMOSFET. To obtain identical surface potentials, the oxide thickness of HfO2 must be larger than SiO2. Unlike SiO2, the minima of surface potential remain constant with channel length for HfO2. The outcome of the TCAD simulation is highly associated with the results of the analytical model. Therefore, to meet high packing density and low power consumption, TGMOSFET can be a potential candidate for ultra large scale integrated circuit (ULSI) technology.

Adsorptive separation of high purity tetramethylsilane on zeolites from low-boiling residues of dimethyldichlorosilane synthesis

Tetramethylsilane (TMS) can be used as an appropriate precursor of fabricating low-k SiCNH barrier layer for ultra large-scale integrated circuits manufacturing. In this work, an efficient and cost-effective method was developed to prepare high valued TMS with more than 99.99 wt% purity via adsorptive separation on zeolite ZSM-5 and 13X adsorbents from the low boiling residues (LBR) of the industrial direct synthesis of dimethyldichlorosilane. The main impurities in LBR mixtures relative to TMS are isopentane and isopentenes (2-methyl-1-butene and 2-methyl-2-butene). The interaction between the molecules and zeolite framework was investigated by breakthrough experiment to understand the adsorption behavior. The adsorption capacity was also determined to evaluate the suitability of the zeolite adsorbents. It was manifested that ZSM-5 zeolite preferentially adsorbed isopentane due to the confinement effect between gas molecule and the zeolite (van der Waals interaction) since the molecular kinetic diameter of isopentane fits well with the pore size of ZSM-5. The selective adsorption of unsaturated isopentenes on zeolite 13X was also observed, which can be explained by the cation-π interaction between the CC double bond and the exchangeable cations of the Al-rich 13X with Brønsted acid sites. Furthermore, the influence of the temperature on the adsorption performance was investigated at various temperatures of 303 K, 313 K and 323 K. An increase in the temperature decreased the time to reach the breakthrough point and the corresponding adsorption capacity. An adsorptive separation experiment was carried out on a binary-adsorbent bed with ZSM-5 and 13X zeolites that can significantly increase the separation of TMS from the LBR mixtures. Finally, high valued TMS with the purity of 99.998 wt% was obtained successfully. The reusability of the zeolite adsorbents was also performed on the binary-adsorbent bed, showing the adsorbents can be fully regenerated for adsorption-regeneration cycling use. Thus, it offers an efficient and great potential route for the separation of high purity TMS from the LBR mixtures for industrial applications.

MODELING OF HYBRID MOS FOR THE IMPLEMENTATION OF SWITCHED CAPACITOR FILTER USING SINGLE ELECTRON TRANSISTOR

In digital integrated circuit architectures, transistors serve as circuit switches to charge and discharge capacitors to the required logic voltage levels. A transistor is a three terminal semiconductor device used to amplify and switch electronic signals and electrical power. It has been observed that the Scaling down of electronic device sizes has been the fundamental strategy for improving the performance of ultra-large-scale integrated circuits (ULSIs). Metaloxide-semiconductor field-effect transistors (MOSFETs) have been the most prevalent electron devices for ULSI applications. A better device will be formed with the help of new technology, with high operating speed low and power consumption, which can be the future of electronics industry. A methodology for the electric simulation of MOS/SET hybrid circuits will be developed. As a result of this, a functional model for the single-electron transistor will obtain and Implement Switched Capacitor Filter with the help of designed hybrid MOS. The SET model can be easily coded in any hardware description language.

SEE Sensitivity Evaluation for Commercial 16 nm SRAM-FPGA

Radiation effects can induce severe and diverse soft errors in digital circuits and systems. A Xilinx commercial 16 nm FinFET static random-access memory (SRAM)-based field-programmable gate array (FPGA) was selected to evaluate the radiation sensitivity and promote the space application of FinFET ultra large-scale integrated circuits (ULSI). Picosecond pulsed laser and high energy heavy ions were employed for irradiation. Before the tests, SRAM-based configure RAMs (CRAMs) were initialized and configured. The 100% embedded block RAMs (BRAMs) were utilized based on the Vivado implementation of the compiled hardware description language. No hard error was observed in both the laser and heavy-ion test. The thresholds for laser-induced single event upset (SEU) were ~3.5 nJ, and the SEU cross-sections were correlated positively to the laser’s energy. Multi-bit upsets were measured in heavy-ion and high-energy laser irradiation. Moreover, latch-up and functional interrupt phenomena were common, especially in the heavy-ion tests. The single event effect results for the 16 nm FinFET process were significant, and some radiation tolerance strategies were required in a radiation environment.

Drain-engineered carbon-nanotube-film field-effect transistors with high performance and ultra-low current leakage

A small bandgap and light carrier effective mass (m0) lead to obvious ambipolar transport behavior in carbon nanotube (CNT) field-effect transistors (FETs), including a high off-state current and severe degradation of the subthreshold swing (SS) with increasing drain bias voltage. We demonstrate a drain-engineered method to cope with this common problem in CNT-film FETs with a sub-µm channel length, i.e., suppressing the ambipolar behavior while maintaining high on-state performance by adopting a feedback gate (FBG) structure to extend the drain region from the CNT/metal contact to the proximate CNT channels to suppress the tunneling current. Sub-400-nm-channel-length FETs with a FBG structure statistically present a high on/off ratio of up to 104 and a sub-200 mV/dec SS under a high drain bias of up to −2 V while maintaining a high on-state current of 0.2 mA/µm or a peak transconductance of 0.2 mS/µm. By lowering the supply voltage to 1.5 V, FBG CNT-film FETs can meet the requirement of standard-performance ultra large scale integrated circuits (ULSICs). Therefore, the introduction of the drain engineering structure enables applications of CNT-film-based FETs in ULSICs and could also be widely extended to other small-bandgap semiconductor-based FETs for an improvement in their off-state property.

Self-Healing Effect of Wet-Processed Organic SAM Diffusion Barrier Layer Using Polymer Capped Palladium Nanoclusters

In ultra-large scale integrated circuits (ULSIs), aluminum (Al) has been replaced by copper (Cu) as the interconnect material due to Cu has higher resistance to electromigration and lower electrical conductivity [1]. Unfortunately, Cu has high mobility in silicon (Si) and silicon dioxide (SiO2), thus impacting interconnect reliability and leading to inferior electrical performance or device failure. Therefore, it is necessary to form a good copper diffusion barrier between Si/SiO2 and Cu layer. In the past few decades, inorganic materials such as tantalum (Ta) or tantalum nitride (TaN) based compounds or metal-alloys has been successfully introduced as the diffusion barrier industrially. However, from the ULSI roadmap revealed by the International Technology Roadmap for Semiconductors report (ITRS), the necessary diffusion barrier thickness for the line-width of 22 nm is less than 2 nm [2], which challenges the current Ta or TaN technology by using the conventional vapor-phase deposition. Recently, a few reports use the organo-silane compounds such as 3-aminopropyltrimethoxysilane (APTMS) as the diffusion barrier to substitute inorganic Ta or TaN barrier layer [3-5], and show promising result. However, forming SAM is known to very sensitive to process conditions, particularly when SAM is prepared by wet-soaking. Imperfect SAM cannot block Cu diffusion efficiently and thus fails to compete with inorganic counterparts. In this study, we developed an all-wet, self-healing process to converge the copper diffusion blocking property on a Cu/SAM/SiO2 substrate. In particular, a 3-[2-(2-aminoethylamino)ethylamino] propyl-trimethoxysilane (ETAS) layer was deposited on SiO2 surface via wet soaking process. Then a 200 nm Cu film was electroless plated onto ETAS-treated SiO2 with the help of a home-made poly(vinyl alcohol)-capped palladium (PVA-Pd) nanoparticle catalysts. By varying ETAS soaking time and the ratio of PVA:Pd in the process, the sheet resistance of the Cu/SAM/SiO2 substrate after rapid thermal annealing (RTA) was investigated. As shown in Fig.1, it can be seen the sheet resistance increased rapidly after RTA over 300 oC in the case of no ETAS treatment, indicating the formation of copper silicide because of the absence of diffusion barrier layer. It is also found in the case of 30 minutes ETAS treatment (approaching SAM[6]) and 1:1 PVA to Pd ratio (ETAS-30-1xPVA-Pd), no copper silicide formation up to 500 oC. Interestingly, in 1 minute ETAS (ETAS-1) soaking samples, which is considered islandish ETAS coating rather than SAM, the PVA:Pd ratio affects the effectiveness of Cu diffusion barrier significantly. The more the PVA, the better Cu diffusion blocking capability is. Finally, in the sample processed by 1 minute islandish ETAS treatment and PVA:Pd ratio of 2 (ETAS-1-2xPVA-Pd), the Cu diffusion blocking capability is identical to the case of ETAS SAM, evidencing PVA can mend the imperfect SAM layer and thus converging the overall performance. Our study provides a simple and controllable process to utilize organic compound as the alternative for Ta or TaN diffusion barrier layer in fine line ULSI fabrication. REFERENCES [1] S. P. Murarka, Mater. Sci. Eng., 19 (1997) 87. [2] International Technology Roadmap for Semiconductors,2013 edition. [3] A. M. Caro, S. Armini, O. Richard, G. Maes, G. Borghs, C. M. Whelan and Y. Travaly, Adv. Funct. Mater., 20 (2010) 1125. [4] W. K. Han, G. H. Hwang, S. J. Hong, C. S. Yoon, J. S. Park, J. K. Cho and S. G. Kang, Appl. Surf. Sci., 255 (2009) 6082. [5] Y. Chung, S. Lee, C. Mahata, J. Seo, S. M. Lim, M. S. Jeong, H. Jung, Y. C. Joo, Y. B. Park, H. Kimd and T. Lee, RSC Adv., 4 (2014) 60123. [6] C. W. Hsu, W. Y. Wang, K. T. Wang, H. A. Chen and T. C. Wei, Sci. Rep., 7 (2017) 1. Figure 1

(Invited) The Mechanism of Surface Modifications of Photoresist Material in Plasma Etching Nano Processes

Etching plasmas employed for the fabrication of ultra large scale integrated circuits (ULSIs) have been causing serious damages to photoresist materials such as surface roughness formations and structural changes. So far, there have been many reports on suppressing these damages by some process techniques such as the UV, HBr plasma cure and so on. However, effects of individual species and photons in the plasma on the damages of photoresist materials have not been clarified enough. Especially, the effect of vacuum ultraviolet (VUV) photons on damages have never been quantitatively understood. Furthermore, beside the VUV photons, the synergetic effects of individual species of ion and radicals enhance the damages. As a result, the chemical structure alteration and the surface roughness formation of polymer materials are considered to be brought about. In the fabrication of the sub-45 nm devices and integrated circuits, it is extremely important to clarify the reaction mechanism of surface modification of photoresist materials induced by the plasma etching process. In this article, firstly, we have focused on the effects of VUV photons on damages on the 193 ArF photoresist materials by investigating the absolute density of VUV photon fluxes measured in the range of 115nm and 200nm in HBr plasma etching processes. The etching and measurement of VUV photons in the plasma were performed in the plasma beam system for understanding the fundamental reaction on the photoresists. This plasma beam system consists of an upper chamber (plasma chamber) and a lower chamber (process chamber). This equipment provided the beam source with the HBr plasma. The plasma beam system was pumped down to a base pressure of 10-5 Pa prior to the experiment. During the whole experiment, inductively coupled plasma (ICP) was generated by applying a radio-frequency (13.56 MHz) power of 400 W to the low-impedance antenna. Pure HBr, H2 or Ar gas was introduced into the plasma chamber at a flow rate of 1 sccm. The pressure of the plasma chamber was maintained at approximately 5 Pa. The chemical compositions of the surface of photoresists before and after the plasma beam irradiation were analyzed by in-situ XPS. On the basis of measured results, effects by VUV photons emitted from HBr on the surface modifications of photoresist materials were clarified. The VUV photons cleaved the MAA groups below the photon dosage of 16 × 1016 photons/cm2. The crosslinking of the photoresist and release of volatile products simultaneously generated the surface roughness. The reaction became saturated with high dosages [1]. Secondary, the sequential irradiation by VUV/radicals from HBr or H2 plasma and Ar ions on a photoresist have been performed. The irradiation by VUV and radicals before the ion irradiation (pre-treatment) suppressed the roughness increase by the ion bombardment but the VUV and radical irradiation after the ion irradiation (post-treatment) increased the roughness. The surface morphologies were also analyzed in detail after pre- or post-treatment on the photoresist by using the power spectral density. Such pre-treatment processes generated a dense and hard crosslinked layers which improved the etch resistance of the photoresist and improved the roughness [2]. The enhancement of roughness by post-treatment was correlated with the removal of the MAA groups and the nonuniformity of crosslinking reactions on the roughened photoresist by the ion irradiation. On the basis of these results, the mechanism of photoresist modifications by individual effects of VUV, ions and radicals and their synergetic effects by sequential irradiation experiments were systematically discussed and then perspectives for the damage less processes to be established in the etching nano processes are introduced. [1] Y. Zhang et al., Journal of Vacuum Science & Technology A, 35, 060606 (2017). [2] Y. Zhang et al., Japanese Journal of Applied Physics, 56, 126503 (2017).

Reaction Mechanisms of Halogenated Silanes on N-Rich Surfaces during Atomic Layer Deposition of Silicon Nitride

Atomic layer deposition (ALD) has recently received increasing attention for the growth of high-conformity silicon nitride (SiN) thin films. In particular, plasma enhanced ALD (PEALD) allows SiN deposition at substantially lower temperatures (< 400 °C) with better film properties, compared to thermal ALD. These advantages make PEALD more attractive for ultra large scale integrated circuit (ULSI) device fabrication where the growth of aspect ratio independent and high-quality conformal thin dielectric films is tremendously important. The PEALD of SiN films involves a repetitive two-step process: (1) adsorption and decomposition of silicon-containing precursors and ii) nitridation of the Si-rich surface by active N species emanating from the plasma. Halogenated silanes such as hexachlorodisilane, bis(tertiary-butyl-amino)- silane, and dicholorosilane (DCS, SiH2Cl2) have been utilized as Si precursors. Despite previous studies, the underlying reaction mechanisms of these Si precursors with a N-rich SiN surface during PEALD still remain uncertain. Parameters controlling the rate of growth and uniformity have been demonstrated experimentally, but without knowledge of the reaction mechanisms, direct contributions of specific process conditions cannot be explained. Using first-principles density functional theory (DFT) calculations combined with experimental characterization, we have examined and identified a novel mechanism for the adsorption and decomposition of DCS on a N-rich SiN surface. Our study predicts that the DCS adsorption and dissociation can occur by overcoming a moderate barrier (~ 0.3 eV), far lower than the prohibitively large barriers predicted for previously proposed mechanisms. Through a detailed electronic structure analysis of the reaction intermediates, we have also elucidated the principles underlying the reaction mechanism, notably the hypervalent nature of Si which permits the facile reaction of molecularly adsorbed DCS with primary and secondary amines on the surface, followed by simultaneous Cl release and deportation steps and subsequent HCl formation and desorption. We have examined the same mechanism utilizing alternative precursors and the predicted trends are found to be corroborated with the important properties of the system. Understanding these principles allows us to develop guidelines for processing conditions, such as the importance of maintaining the proper surface composition to facilitate Si precursor adsorption and dissociation. Our study provides insight into the SiN ALD process via chlorosilanes and guidelines to control the deposition for high-quality SiN films and provides a framework for future theoretical studies of surface reactions during ALD.

Properties of Annealed ALD Ru from Ru(DMBD)(CO)3 and Oxygen

Ruthenium metal has a low bulk resistivity (7.1 μΩ cm), a high work function (4.7 eV), and a low solid solubility with strong adhesion to Cu, and is etchable, making Ru an attractive barrier metal or seed layer for Cu electroplating.1 For these applications, conformal deposition on the high-aspect ratio structures encountered in the back end of line (BEOL) of ultra largescale integration (ULSI) circuits is required. Atomic layer deposition (ALD), based on purge-separated dosing of precursors and self-saturating surface reactions, allows for atomic scale control and inherent high conformality. Because of these advantages, ALD processes for Ru are strongly desired. Although a number of ALD processes for Ru have been reported, currently the most widely reported Ru ALD precursor, Ru(EtCp)2, as well as other non-zero oxidation state precursors show long nucleation delays (~ 200 ALD cycles) prior to film growth. As nucleation delays can result in island growth and increased roughness and Ru films used in ULSI applications are generally only a few to tens of nanometers thick, nucleation delay is a critical growth parameter. More recent work has shown that zero oxidation state Ru precursors can significantly reduce nucleation delays for O2-based thermal ALD processes. However, the resistivities of these films are generally 18-40 µ-ohm cm, well above the bulk value. Very recently, a zero oxidation state ALD Ru process based on η4-2,3- dimethylbutadiene ruthenium tricarbonyl [Ru(DMBD)(CO)3] and O2, showed zero nucleation delay, a surface roughness of 0.6 nm RMS, and a resistivity of 14 µΩ-cm.2 Although the resistivity of films deposited using this Ru(DMBD)(CO)3 / O2 process is among the lowest values reported for ALD Ru, it still larger than the resistivity of pure ruthenium. It was speculated that residual oxygen resident in the film was the cause of the higher than bulk resistivity. In this work, we investigate the impact of annealing on the structure and electronic properties of ALD Ru. ALD Ru was deposited on either Si or Si/SiO2 substrates in a Picosun R-200 SunALE reactor at 260˚C using pure separated pulses of Ru(DMBD)(CO)3 & O2. Ru films were annealed in a reducing forming gas (4% H2 in N2) environment as well as an inert pure N2 environment at 400, 450, and 500C for various times. Resistivity is characterized via 4-pt probe, roughness via atomic force microscopy (AFM, crystallite size via x-ray diffraction (XRD), thickness and density via x-ray reflectivity (XRR), and composition via x-ray photoelectron spectroscopy (XPS). In addition, ruthenium-insulator-semiconductor (MOS) capacitors were used to extract the effective work function of the Ru. We find that post-deposition annealing reduces resistivity. For 500 C annealing in a 4% H2 / N2 ambient, resistivity was reduced from an as-deposited value of ~15 µΩ-cm to less than 10 µΩ-cm after 30 minutes and ~9 µΩ-cm after 60 mi, closely approaching the bulk value. These results indicate that ALD of Ru using Ru(DMBD)(CO)3 & O2 appears very promising for microelectronics applications. R. W. Powell, R. P. Tye, and J. Woodman Margaret, Platin. Met. Rev., 6, 138–143 (1962).D. Z. Austin et al., Chem. Mater., 29, 1107–1115 (2017).

Research advances of electrochemical micro/nanofabrication based on confined etchant layer technique

Compared with mechanical machining, ECM has several advantages, such as avoiding tool wear, none thermal or mechanical stress on machining surfaces, as well as high removal rate. Moreover, ECM is capable of making complex three-dimensional structures and is appropriate for flexible, fragile, or fissile materials even materials harder than the machining tool. Thus, ECM has been widely used for various industrial applications in the fields of aerospace, automobiles, electronics, etc. ECM methods can be classified usually as electrolytic machining based on anodic dissolution and electroforming based on cathodic deposition of metallic materials. Recently, high technology industry, such as ultralarge scale integration (ULSI) circuits, microelectromechanical systems (MEMS), miniaturized total analysis systems (μ-TAS) and precision optics, has developed more and more rapidly, where miniaturization and integration of functional components are becoming significant. Nowadays, the feature size of interconnectors in ULSI circuits has been down to 20 nanometers, predicted by Moore’s law. Confined etchant layer technique (CELT) was proposed in 1992 to fabricate three-dimensional micro- and nanostructures (3D-MNS) on different metals and semiconductors, which has been developed an effective machining method with independent intellectual property rights. Generally, there are three procedures in CELT: (1) generating the etchant on the surface of the tool electrode by electrochemical or photoelectrochemical reactions; (2) confining the etchant in a depleted layer with a thickness of micro- or nanometer scale; (3) etching process when the tool electrode is fed to the workpiece, which applicable for 1D milling, 2D polishing, and 3D microfabrication with an accuracy at micro or nanometer scale. External physical-field modulations have recently been introduced into CELT to improve its machining precision. In this review, the advances of CELT in principles, instruments and applications will be addressed as well as the prospects.

Confined Chemical Etching for Electrochemical Machining with Nanoscale Accuracy.

In the past several decades, electrochemical machining (ECM) has enjoyed the reputation of a powerful technique in the manufacturing industry. Conventional ECM methods can be classified as electrolytic machining and electroforming: the former is based on anodic dissolution and the latter is based on cathodic deposition of metallic materials. Strikingly, ECM possesses several advantages over mechanical machining, such as high removal rate, the capability of making complex three-dimensional structures, and the practicability for difficult-to-cut materials. Additionally, ECM avoids tool wear and thermal or mechanical stress on machining surfaces. Thus, ECM is widely used for various industrial applications in the fields of aerospace, automobiles, electronics, etc. Nowadays, miniaturization and integration of functional components are becoming significant in ultralarge scale integration (ULSI) circuits, microelectromechanical systems (MEMS), and miniaturized total analysis systems (μ-TAS). As predicted by Moore's law, the feature size of interconnectors in ULSI circuits are down to several nanometers. In this Account, we present our perseverant research in the last two decades on how to "confine" the ECM processes to occur at micrometer or even nanometer scale, that is, to ensure ECM with nanoscale accuracy. We have been developing the confined etchant layer technique (CELT) to fabricate three-dimensional micro- and nanostructures (3D-MNS) on different metals and semiconductor materials since 1992. In general, there are three procedures in CELT: (1) generating the etchant on the surface of the tool electrode by electrochemical or photoelectrochemical reactions; (2) confining the etchant in a depleted layer with a thickness of micro- or nanometer scale; (3) feeding the tool electrode to etch the workpiece. Scavengers, which can react with the etchant, are usually adopted to form a confined etchant layer. Through the subsequent homogeneous reaction between the scavenger and the photo- or electrogenerated etchant in the electrolyte solution, the diffusion distance of the etchant is confined to micro- or nanometer scale, which ensures the nanoscale accuracy of electrochemical machining. To focus on the "confinement" of chemical etching reactions, external physical-field modulations have recently been introduced into CELT by introducing various factors such as light field, force field, hydrodynamics, and so on. Meanwhile, kinetic investigations of the confined chemical etching (CCE) systems are established based on the finite element analysis and simulations. Based on the obtained kinetic parameters, the machining accuracy is tunable and well controlled. CELT is now applicable for 1D milling, 2D polishing, and 3D microfabrication with an accuracy at nanometer scale. CELT not only inherits all the advantages of electrochemical machining but also provides advantages over photolithography and nanoimprint for its applicability to different functional materials without involving any photocuring and thermoplastic resists. Although there are some technical problems, for example, mass transfer and balance, which need to be solved, CELT has shown its prospective competitiveness in electrochemical micromachining, especially in the semiconductor industry.

Formation of large-grain crystalline germanium on single layer graphene on insulator by rapid melting growth

We demonstrate the crystallization of thermally deposited amorphous germanium (Ge) microstrips on single layer graphene (SLG) by rapid melting growth. Lateral growth of large grain crystalline Ge was successfully obtained over entire microstrip structure. SLG has shown its capability to suppress the spontaneous nucleation in the melting Ge, where no or less intermixing of C and Ge atoms has been detected. The interaction of C atoms from the graphene and Ge atoms at the interface is the possible reason for the observation of large compressive strain generated in the Ge strip grown on SLG. This technique provides an innovative breakthrough towards the realization of single-crystalline Ge-on-insulator (GOI) structure on SLG to facilitate the next-generation ultra-large-scale integrated circuits (ULSIs) with multifunctionalities.

Etching Studies of BCN Thin Films

The ever increasing advancements in semiconductor technology and continuous scaling of CMOS devices mandate the need for new dielectric materials with low-k values. The interconnect delay can be reduced not only by the resistance of the conductor but also by decreasing the capacitance of dielectric layer. Also cross-talk is a major issue faced by semiconductor industry due to high value of k of the inter-dielectric layer (IDL) in a multilevel wiring scheme in Si ultra large scale integrated circuit (ULSI) devices. Recently it has been found that Boron Nitride (BN) films can achieve low-k values around and hardness comparable to diamond [1][2]. BN is hygroscopic in nature. In this respect carbon can be added to the BN structure to produce Boron Carbon Nitride (BCN) films as the possible substitute for BN. The minimum dielectric constant achieved by plasma assisted chemical vapor deposition for a BCN thin film was reported to be 1.9. [2] The BCN films are also instrumental in suppressing the Cu migration [3]. The Young’s modulus of BCN films are reported well above 20 GPa making it one of the suitable options for low-k materials [4]. In the present work, BCN films were deposited by dual target sputtering of boron carbide (BC) target (DC), boron nitride (BN) target (RF) in nitrogen ambient with argon. The films were deposited under various N­2/Ar gas flow ratios and temperature. BCN is etched using an etchant that consists of 16 parts of Phosphoric acid (H3PO4), 1 part of Nitric acid (HNO3), 1 part of Acetic acid (CH3COOH), 20 parts of DI water. Various plots of etch rates with respect to deposition parameters and Arrhenius plots are studied. REFERENCES [1] Jun Liu, Kian Ping Loh, Ming Lin, Yong Lim Foo, Wei De Wang, and Dong Zhi Ch, Journal of Applied Physics, 96 (2004) 6679. [2] Riedel R., Advanced Materials, 4 (1992) 759. [3] M. K Mazumder, R. Moriyama, D. Watanabe, C. Kimura, H. Aoki, and T. Sugino: Jpn. J. Appl. Phys. 46 (2007) 2006. [4] C. Morant, D. Caceres, J. M. Sanz, and E. Elizalde: Diamond Relat. Mater. 16 (2007) 1441.

Formation of germanium (111) on graphene on insulator by rapid melting growth for novel germanium-on-insulator structure

We demonstrate the crystallization of the microstrips of electrodeposited amorphous germanium (Ge) on graphene on insulator by rapid melting growth for the first time. Growth of single-crystalline Ge microstrips with (111) orientation was confirmed. The high level of compressive strain was found to be resulted from the intermixing of C atoms from multilayer graphene (MLG) and Ge. Probably the introduction of local C atom into Ge film enhances nucleation of Ge on MLG, which results in (111)-oriented Ge nuclei. Subsequent lateral growth enables crystallization of Ge with (111) orientation on the entire microstrip. The results also indicate that graphene is very useful to suppress the spontaneous nucleation in the melting Ge films and the lattice rotation or misorientation. This novel and innovative technique provides a breakthrough towards the realization of high quality Ge-on-insulator structures to facilitate the next-generation ultra-large-scale integrated circuits (ULSIs) with multifunctionalities.

Development of methods for calculating basic features of the nuclear contribution to single event upsets under the effect of protons of moderately high energy

As a continuation and a development of previous studies of our group that were devoted to the investigation of nuclear reactions induced by protons of moderately high energy (between 10 and 400 MeV) in silicon, aluminum, and tungsten atoms, the results obtained by exploring nuclear reactions on atoms of copper, which is among the most important components in materials for contact pads and pathways in modern and future ultralarge-scale integration circuits, especially in three-dimensional topology, are reported in the present article. The nuclear reactions in question lead to the formation of the mass and charge spectra of recoil nuclei ranging fromheavy target nuclei down to helium and hydrogen. The kineticenergy spectra of reaction products are calculated. The results of the calculations based on the procedure developed by our group are compared with the results of calculations and experiments performed by other authors.

Preparation and characterization of nanoporous polyimide membrane by the template method as low-k dielectric material

In order to decrease the resistance–capacitance delay and signal crosstalk in ultra large-scale integrated circuits (ULSIC), dielectric materials with ultra low dielectric constants are developed to be the replacement of silicon dioxide. Introduction of air on the matrix material is an important method to reduce the dielectric constant, and polyimide (PI) is the most promising polymer to prepare porous matrix material for its distinct advantages. PI membrane with nanopores was prepared by the method of template method (i.e. thermolysis of polystyrene nanospheres in the matrix) following the synthesis of template. The nanoporous membrane was characterized by Fourier transformer infrared, scanning electron microscopy, thermogravimetric analysis, and the dielectric constant of which was measured. Results showed that uniform nanopores about 100–200 nm were formed in the PI membrane, and dielectric constant of which was decreased to 2.08 from 3.34. The nanoporous membrane can be applied as potential low-k dielectric material in ULSIC. Copyright © 2015 John Wiley & Sons, Ltd.

XPS and FTIR Studies of Dual Target Sputtered Bcn Thin Films

The ever increasing advancements in semiconductor technology and continuous scaling of CMOS devices mandate the need for new dielectric materials with low-k values. The interconnect delay can be reduced not only by the resistance of the conductor but also by decreasing the capacitance of dielectric layer. Also cross-talk is a major issue faced by semiconductor industry due to high value of k of the inter-dielectric layer (IDL) in a multilevel wiring scheme in Si ultra large scale integrated circuit (ULSI) devices. Recently it has been found that Boron Nitride (BN) films can achieve low-k values around and hardness comparable to diamond [1][2]. BN is hygroscopic in nature. In this respect carbon can be added to the BN structure to produce Boron Carbon Nitride (BCN) films as the possible substitute for BN. The minimum dielectric constant achieved by plasma assisted chemical vapor deposition for a BCN thin film was reported to be 1.9. [2] The BCN films are also instrumental in suppressing the Cu migration [3]. The Young’s modulus of BCN films are reported well above 20 GPa making it one of the suitable options for low-k materials [4]. In the present work, BCN films were deposited by dual target sputtering of boron carbide (BC) target (DC), boron nitride (BN) target (RF) in nitrogen ambient with argon. The films were deposited under various N­2/Ar gas flow ratios and temperature. XPS and FTIR measurements were performed to find the relative chemical compositions, chemical bonds and behavior of the deposited films with respect to change in N­2/Ar gas flow ratios and deposition temperature. REFERENCES [1] Jun Liu, Kian Ping Loh, Ming Lin, Yong Lim Foo, Wei De Wang, and Dong Zhi Ch, Journal of Applied Physics, 96 (2004) 6679. [2] Riedel R., Advanced Materials, 4 (1992) 759. [3] M. K Mazumder, R. Moriyama, D. Watanabe, C. Kimura, H. Aoki, and T. Sugino: Jpn. J. Appl. Phys. 46 (2007) 2006. [4] C. Morant, D. Caceres, J. M. Sanz, and E. Elizalde: Diamond Relat. Mater. 16 (2007) 1441.