Ultra-wideband Low Noise Amplifier Research Articles

Graphical Design Approach for UWB Stacked CG LNA Using Inversion Coefficient

The design of ultra-wide-band (UWB) low-noise amplifiers (LNAs) entails a large number of design challenges and tradeoffs, which include sustaining good input matching over a wide bandwidth along with finding a proper compromise between various LNA performance metrics, such as gain, bandwidth, noise figure, power, and linearity. This paper presents a design approach for UWB LNAs based on the inversion coefficient (IC). The proposed approach is a graphical design approach where the proper operating point is chosen based on predefined constraints. A complete systematic solution is presented for the problem of UWB input matching with a high degree of analytical accuracy. The design approach is illustrated through the design of two UWB stacked common-gate LNAs in 65 nm technology. The post-layout simulation results show very good agreement with analytical expectations. The first LNA achieves an S11 better than −8.2 dB over a 27.6 GHz frequency range, a gain of 12.4 dB over a 16.5 GHz bandwidth, a minimum noise-figure, NF, of 4.5 dB, and an IIP3 of −5.2 dBm while consuming only 530 μW. The second LNA achieves an S11 better than −15 dB over an 8.8 GHz frequency range, a gain of 12.5 dB over a 6.8 GHz bandwidth, a minimum NF of 4 dB, and an IIP3 of −4.3 dBm while consuming only 550 μW.

Ultra-wideband low noise amplifier using resistive feedback and current reause

Ultra-wideband low noise amplifier using resistive feedback and current reause

An Ultra-wideband Low-power Low-noise Amplifier Linearized by Adjusted Derivative Superposition and Feedback Techniques

Ultra-wideband (UWB) applications require low-power and low-noise amplifiers (LNAs) that can operate over a wide frequency range. However, conventional LNAs often suffer from poor linearity and high-power consumption. This research work proposes a novel LNA design that uses the adjusted derivative superposition (DS) technique and feedback to improve the linearity and reduce the power consumption of UWB LNAs. The DS technique enhances the third-order intermodulation (IM3) cancellation by adjusting the bias currents of the transistors, whereas the feedback improves the stability and input matching of the LNA. The LNA is implemented using a degenerated common source topology in a 180 nm standard CMOS technology. The simulation results show that the LNA achieves a power gain of 10–12.2 dB, an input third-order intercept point (IIP3) of about 12 dBm, and a noise figure of less than 2.5 dB over the UWB frequency band of 3.1–10.6 GHz. The input reflection coefficient is less than -10 dB, and the power consumption is 11.6 mW with a 1.5 V power supply. The designed LNA offers a novel and innovative solution for UWB applications that significantly improve the performance and efficiency of UWB LNAs whereas reducing the cost and complexity of implementation.

An ultra-wideband low noise amplifier with cascaded flipped-active inductor for cognitive radio applications

Cognitive radio (CR) is an ultra-wideband communication system with a 50 MHz to 10 GHz frequency band that intelligently optimizes the use of the available frequency spectrum using dynamic spectrum monitoring. This paper proposes a differential ultra-wideband low-noise amplifier using two cascaded flipped-active inductors (CASFAI-LNA). The structure of each CASFAI consists of two transistors (gyrator-capacitor) and a common gate pMOS in its feedback path. The use of the capacitor cross-coupling method increases the transconductance of the circuit, which in addition to improving the gain and the noise figure, reduces the current consumption of the circuit. In addition, the biasing of active inductors from the feedback path reduces the power consumption of the circuit. This circuit is designed and validated in Cadence using a 0.18 μm CMOS process. The post-layout simulation results show that in the whole desired bandwidth (CR frequency range), the input matching is better than −10 dB, the maximum power gain is higher than 10.6 dB, the minimum noise figure is 2.24 dB, the stability factor is higher than 2.8, and the maximum IIP3 is −2.3 dBm. The proposed LNA consumes 6.12 mW from a 1.8 V DC supply.

On the Coupling Imbalance of the UWB BLC in the 5G Low Noise Amplifier Design

In this article, the design and the development of ultra-wideband UWB branch-line couplers BLCs with a novel method to control the coupling imbalance are proposed. The proposed UWB BLC is suitable for the 5G low-noise amplifier (LNA) design. UWB 4-branch BLC is designed using design curves developed using even and odd mode analyses to cover the 5G (3.3-5 GHz) frequency bands. The vertical branches of the UWB BLC are replaced by modified ones, and their effect on the coupling imbalance is investigated. The proposed BLC occupies an area of 33.9 × 15.7 mm2 Both conventional and modified BLC are fabricated, and their measured S-parameters are compared with analytical and simulated models. Based on the balanced amplifier topology, a 5G UWB low-noise amplifier is designed. The proposed BLCs and the MGF3022AM InGaP-HBT (Heterojunction Bipolar Transistor) are used to produce acceptable UWB performance. The balanced amplifier return loss, noise figure, and gain are investigated as BLCs coupling imbalance varies. The ultra-wideband LNA exhibits an acceptable small-signal gain, noise figure, input return loss, and output return loss across the 5G different frequency bands.

Ultra-wideband Low-Noise Amplifier with Tunable Bandwidth

Ultra-wideband Low-Noise Amplifier with Tunable Bandwidth

Ultra-wideband Reconfigurable Low-noise Amplifier Based on 5G Communication

For 5G communication, both sub-6G and millimeter wave bands have their own advantages, while low-noise amplifier (LNA) is an essential component of the first stage of 5G receiving system, and its performance plays a crucial role in the overall performance of the receiving system. Therefore, LNAs applicable to ultra-wideband reconfigurable can make full use of both high and low frequency bands, which is one of the research focuses of 5G communication development at this stage. In this paper introduces ultra-wideband low-noise amplifiers and their methods of achieving reconfigurability, explaining the development advantages and limitations of each method separately.

Design of an ultra-wideband LNA using transformer matching method

A new transformer matching method for ultra-wideband (UWB) low noise amplifier is presented, which effectively extends the bandwidth and has little effect on the circuit noise. Low-frequency gain compression are realized by combining Frlan-style transformer and RC feedback loop topology in the interstage. The output matching network is composed of the Rabjohn-style transformer and LC network after Norton transformation. The power gain is enhanced by using two-stage cascode topology. The proposed UWB LNA is based on a 0.25um GaAs PHEMT process, and the post-layout simulation results show the maximum power gain of 21 dB, minimum NF of 1.6 dB in the frequency range of 4–15 GHz. The input reflection coefficient is less than -7dB. The output reflection coefficient is less than −10dB. The average output 1-dB compression point is 14dBm. The chip size is 0.82 mm2.

Design and simulation of 1.2 mW power consumption ultra-wideband low noise amplifier for ultra-wideband wireless communications

design and simulation of 1.2 mW power consumption ultra-wideband low noise amplifier for ultra-wideband wireless communications

A high linearity low power low-noise amplifier designed for ultra-wide-band receivers

This paper presents a new ultra-wide band (UWB) CMOS low noise amplifier (LNA) with very high linearity and low power consumption for UWB wireless communication applications, where linearity is a big challenge, due to presence of interference and blocker signals, as well as the in-band harmonics of the desired signal components in the lower part of UWB band. The proposed LNA uses a new combination of saturated NMOS and PMOS transistors to improve both of second order and third order nonlinearities, meanwhile improving the noise performance and DC power consumption. In our design two techniques are integrated in a novel approach: Improved Complementary Derivative Superposition (ICDS) technique and Forward Body Bias (FBB) to reduce the threshold voltage of MOSFET, and hence, lowering the DC power. By utilizing a high-pass filter and common source stage in cascode form, wideband impedance matching and optimal noise figure (NF) have been obtained in the proposed UWB–LNA. The Post-layout simulation of the linearized LNA in a 180 nm RF CMOS process shows NF between 2.5 and 4 dB, gain of 10.8 ± 0.5 dB, and S11 less than −10 dB in the entire 3.1–10.6 GHz band. Total DC power consumption is only 6 mW with 1.2 V supply voltage. The average and the maximum of IIP3 in the UWB band are + 3.84 dBm and + 7.27 dBm, respectively, a superior linearity performance compared to the reported UWB ones. The chip area is 926 mm × 1075 mm, including the supply and ESD ring and the pads.

Flat-High-Gain Design and Noise Optimization in SiGe Low-Noise Amplifier for S–K Band Applications

This paper presents an ultra-wideband (UWB) low-noise amplifier (LNA) with extremely flat-high-gain and low-noise figure (NF). In traditional resistive feedback topology, input matching, gain, and NF cannot be balanced. For better performance trade-offs in UWB design, a novel emitter-follower resistive feedback (EFRFB) is introduced, which utilizes a common-collector amplifier followed by a feedback resistor to flatten the gain (the ripple reduced by 2.3 dB) while alleviating the constraints between the gain and input matching. The enhanced gain without restraint by S11 is exactly required for noise reduction technology. Moreover, a peaking inductor and two resistors are adopted to improve bandwidth and output matching, respectively. The proposed LNA is implemented in a 0.18-μm SiGe BiCMOS technology and occupies 0.15 mm2 without pads. Measurements demonstrate that the LNA has a gain of 19.5 dB with ripple < 0.6 dB, a minimum NF of 2.8 dB from 2 to 22 GHz, and an input third-order intercept point (IIP3) of–7.6 dBm at 10 GHz while drawing 10.9 mA from a 3.3 V supply.

Design and Analysis of Simultaneous Wideband Input/Output Matching Technique for Ultra-Wideband Amplifier

A simultaneous wideband input/output matching technique for ultra-wideband (UWB) low-noise amplifier (LNA) is proposed in this paper. Feedback resistors leading the gate inductors combined with inductive dividers at output ports achieve an extended bandwidth and good input/output return loss. Moreover, Q-factor improved vertical solenoid inductors are used in the matching networks for high gain and low noise figure (NF). The proposed matching technique, not only enhances the bandwidth, but also achieves a high gain and a low NF for the fabricated 3.1-10.6-GHz monolithic 180-nm CMOS UWB amplifier. Operating at low supply voltage, the measured power consumption is 18.9 mW, the measured gain of the UWB LNA is 15.02 dB, and the NF is 3.1 dB. Moreover, the measured input/output reflection coefficients S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> and S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">22</sub> are lower than -9.4 dB and -15.8 dB, respectively, covering the full-band UWB frequencies. Compared to previously published full-band 3.1-10.6-GHz 180-nm CMOS UWB LNAs, the proposed LNA measurements demonstrate high gain, low NF, low supply voltage, low power dissipation, and good input/output reflection coefficients.

High gain 0.18 μm-GaAs MMIC cascode-distributed low-noise amplifier for UWB application

This paper describes a design of 3 GHz–12 GHz MMIC distributed Low Noise Amplifiers (LNAs) for Ultra Wideband communications systems. The proposed circuit is a common source and cascode topology using a standard 0.18 μm ED02AH process from OMMIC foundry. The ultra-wideband LNA achieves a power gain of 16.9 ± 1.7 dB and an average noise figure of 2.9 ± 0.58 dB. The input and output reflection coefficients are less than −10 dB, the reverse gain S12 is less than −37dB and a high linearity IIP3 of [4–6.2] dBm. The chip area including testing pads is only about 1.3 × 1.3 mm2.

Design of a high linear and ultra-wideband LNA using post distortion star feedback method

In this paper, a CMOS low noise amplifier (LNA) with very high linearization for ultra-wideband (UWB) applications is presented. In the proposed LNA, both second- and third-intercept points (IIP2 and IIP3) are improved by the new suggested post distortion star feedback (PDSF) technique in a wide frequency range. The star feedback circuit consists of three resistors that eliminate the nonlinear effect of the cascade transistor, and the PD circuit has an auxiliary transistor that eliminates the third-order non-linear coefficient of the main transistor. The post-layout simulation results of the proposed UWB LNA, which is designed using TSMC RF CMOS 65 ​nm, show the maximum power gain of 11 ​dB, minimum NF of 3.2 ​dB, and average IIP3 of 24 dBm in the frequency range of 3.1–10.6 ​GHz. In the designed circuit, the maximum IIP2 of 23.4 dBm is achieved. The chip area of the circuit is 0.874 ​mm2, while the LNA consumes 15 ​mW from a 1.2 ​V supply voltage.

An Ultra-Wideband 0.1–6.1 GHz Low Noise Amplifier in 180 nm CMOS Technology

In this paper, an Ultra-Wideband (UWB) low noise amplifier (LNA) with low power consumption and high-power gain in 180[Formula: see text]nm CMOS technology is presented. An innovative combination of conventional methods to design UWB-LNA, i.e., resistive-feedback, inductive-series peaking, noise cancelling and inductive degeneration techniques is described here. The proposed LNA consists of two common source amplifiers with resistive feedback in which the noise and power consumption have been reduced by using the noise cancelling and current reuse techniques, respectively. Also, resistive feedback in the first stage reduces input resistance, hereby improving input impedance matching. In the second stage, which is used to increase the power gain, a common source structure with inductive-series peaking and noise cancellation techniques is used. The analytical results agree well with the post layout simulation results. The post-layout simulation shows a gain of [Formula: see text][Formula: see text]dB and noise figure (NF) of 2.3[Formula: see text]dB in the whole [Formula: see text][Formula: see text]dB bandwidth of 0.1[Formula: see text]GHz to 6.1[Formula: see text]GHz, while the S11 and S22 are less than [Formula: see text][Formula: see text]dB. The proposed circuit has a figure of merit of 9.9 which is significantly improved compared to the previous works. The total power dissipation is only 7.3[Formula: see text]mW, and the active area is less than 0.7[Formula: see text]mm2.

3‐5 GHz multifinger CMOS LNA using a simultaneous noise and impedance matching technique by a significant reduction of broadband impedance variation of metal–oxide–semiconductor field effect transistor

This work provides a new simultaneous noise and impedance matching (SNIM) methodology for designing a 3–5 GHz ultrawideband low-noise amplifier (LNA) in 0.18 μm complementary metal–oxide–semiconductor (CMOS) process using the advanced design system platform. To justify the proposed method, common gate (CG)- and common source (CS)-input-matched LNAs are designed where the variation of input impedance over the whole operating band is significantly reduced by applying the multifinger layout technique and employing shunt passive elements for the input device without degenerating the structure, respectively. As part of the proposed SNIM method, a two-dimensional contour plot-based process variation tolerant bias voltage set up protocol is developed which can optimise forward gain (S21), noise figure (NF) and stability factor simultaneously. The regulation of amplifier port parameters with bias settling contour plots and finger parameters results in the proposed SNIM technique. For the CG-input-matched LNA, the post-layout electromagnetic simulated NF is between 3.08 and 4.1 dB, the average power gain of 25.52 dB with a power consumption of 20.19 mW and the CS-input-matched LNA achieves an NF in between 2.772 and 3.04 dB, the average power gain of 17.98 dB while the dissipated power is 20.73 mW.

Ultra‐wideband complementary metal‐oxide semiconductor low noise amplifier using CS‐CG noise‐cancellation and dual resonance network techniques

In this paper, a low power ultra-wideband (UWB) low noise amplifier (LNA) with high and flat voltage gain is proposed using CS-CG noise-cancellation and dual resonance network techniques based on TSMC 180 nm technology. The CS-CG noise cancellation technique reduced the noise figure in 3-10.6 GHz frequency band, and the dual resonance network technique is applied to reach an acceptable input matching. In order to reduce the number of inductors, the active inductor is used in the noise cancellation stage. Also, to control voltage gain and input return loss, a resistor is connected in parallel to channel length modulation resistance of the transistor in the first stage. The developed LNA circuit provides a high and flat voltage gain of 12.75 dB with 0.65 dB variation, which is the result of using two stages common-source topology. An average noise figure of 2 dB, with its maximum value of 2.3 dB, an IIP3 of -8 dBm are obtained from 3 to 10.6 GHz, respectively. The obtained input and output matching value are better than -10 dB. The layout of proposed LNA occupies an area of 0.55 mm2 including ring pad and this structure consumes 11.56 mW from 1-V dc supply.

A 5.7 mW, UWB LNA for Wireless Applications Using Noise Canceling Technique in 90 nm CMOS

AbstractA 3–12 GHz ultra-wideband (UWB) low noise amplifier (LNA) is proposed in this paper. The first stage common-gate (CG), common-source (CS) noise canceling approach is used to achieve low noise-figure (NF). CG configuration at the input stage provides wideband input-matching. The noise of CG transistor is cancelled by systematically added two parallel CS transistors, whose outputs are cascoded in second stage. In order to achieve flat power gain (S21) response, a series peaking inductor is used in the second stage. The proposed LNA is designed in 90 nm CMOS process with chip-layout area of 0.467 mm2 and in comparison to the existing LNAs, it consumes a low power of 5.7 mW from a 1 V supply. The achieved input-reflection coefficient (S11) is &lt;−7.5 dB, output-reflection coefficient (S22) is &lt;−7.6 dB with NF &lt; 5.8 dB for 3–12 GHz UWB and third-order intercept point (IIP3) of −19 dBm. It achieves high and flat S21 of 20.84 ± 0.28 dB over 4.2–10 GHz, with NF ranging from 2.6–3.6 dB.

A band-selective CMOS low-noise amplifier with current reuse gm boosting technique for 3-5 GHz UWB receivers

The authors have proposed a 3-5 GHz ultra-wideband (UWB) low power and low noise amplifier (LNA) with the TSMC 0.18 μm RF CMOS process, which uses a novel dual input matching network for wideband matching. We have used a current-reuse gm-boosted common-gate topology and shunt-shunt feedback common-source output buffer to improve gain and noise figure with low power dissipation. The proposed dual input matching gm-boosted common-gate LNA has been efficient bandwidth to cover UWB band. It has required less inductors or amplification stages to increase bandwidth as compared with the conventional UWB common-gate LNAs. The broadband input stage has been able to be switched to three frequency bands with capacitive switches. The capacitive switch has replaced a large inductor to resonate at lower frequency band. The band-selective LNA has shown linearity improvement by attenuating the undesired interference of a wideband gain circuit and using less inductors. Simulated performance has shown the gains of 15.9, 17.6, and 16.9 dB, and the noise figures of 3.38, 3.28, and 3.27 dB at the 3.432, 3.960, and 4.488 GHz frequency bands, respectively. The proposed UWB LNA has consumed 5 mW from a 1.8-V power supply.

A 2.99 dB NF 15.6 dB Gain 3-10GHz Ultra-wideband low-noise amplifier for UWB systems in 65 nm CMOS

A low noise figure (NF) and high power gain (S21) 3–10 GHz ultra-wideband (UWB) low noise amplifier (LNA) in 65 nm CMOS technology is proposed for UWB system which has a high figure of merit. A shunt–shunt resistive feedback technique is used to achieve wideband input impedance matching. A differential current-reused structure is used to achieve high common noise suppression and low power consumption. The implemented LNA achieves a high and flat aS21 of 15.6 ± 1.07 dB with an input return loss (S11) which is better than − 8.7 dB and a low NF of 2.99 ± 0.18 dB at frequencies of 3–10 GHz. The measured input third-order intermodulation point (IIP3) is − 5.7 dBm at 6 GHz.