Ultra-wideband Low Noise Amplifier Research Articles

Analysis of Active Feedback and its Influence on UWB Low Noise Amplifier

this paper, various active feedback techniques for Ultra- Wide Band (UWB) CMOS Low Noise Amplifier (LNA) are proposed. First, an LNA consisting of Common Gate (CG) stage for input matching, cascode with interstage current reuse as core stage and Common Drain (CD) stage for output matching is presented. Three feedback techniques such as global feedback, local full feedback and local partial feedback techniques are employed in this LNA. The analysis is made for the different feedback networks consisting of resistive, common source, common gate and common drain. The proposed LNA is designed with 90 nm technology and its performance is analyzed with Agilent's ADS simulator. Among the analyzed LNA's, CG partial active feedback and CD partial active feedback achieves power gain of 23.8 dB and 23.75 and noise figure of 6.1-6.3 dB and 4.6-5.8 dB respectively.

High-Performance Wideband Low-Noise Amplifier Using Enhanced $\pi$-Match Input Network

A low noise-figure (NF) and high power gain (S21) 3 ~ 10 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity using 0.18 μm CMOS technology is reported. An enhanced π-match input network is used to achieve wideband input impedance matching as well as high and flat S21. To achieve low and flat NF, the pole frequency and pole quality factor of the second-order NF frequency response are tuned to approximate the maximally flat condition. The LNA consumes 18 mW, achieving S11 better than -10 dB for frequency lower than 12.2 GHz and group-delay (GD) variation smaller than ±14.6 ps for frequencies 3 ~ 10 GHz. Additionally, high and flat S21 of 13.7 ± 1.5 dB is achieved for frequencies 1 ~ 12.5 GHz, which means the corresponding 3-dB bandwidth is 11.5 GHz. Furthermore, the LNA achieves minimum NF of 2.2 dB at 4 GHz and NF of 2.3 ± 0.1 dB for frequencies of 3 ~ 10 GHz, one of the best NF results ever reported for a 3 ~ 10 GHz CMOS LNA.

30–50 GHz high‐gain CMOS UWB LNA

A 30–50 GHz CMOS ultra-wideband (UWB) low-noise amplifier (LNA) with a flat high power gain (S21), along with a flat low-noise figure (NF) is demonstrated for the Atacama large millimetre array (ALMA) band-1 (31.3–45 GHz) system applications. The high S21 and low NF are achieved because the triple-well transistors are utilised with their respective source and body terminals connected together. Furthermore, the bandwidth extension and gain flatness is achieved due to the careful design of the inductive-peaking networks. The LNA has a measured S21 of 21.5 ± 1.5 dB, a minimum NF (NFmin) of 3.8 dB at 32.5 GHz, an average NF (NFavg) of 4.67 dB over the range of 30–50 GHz and an input third-order intercept point (IIP3) of 0 dBm, with a DC power consumption of 20.4 mW at 1.2 V supply. The proposed LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain bandwidth product and highest IIP3 suitable for the ALMA band-1 system applications.

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6GHz. The resonance points were set in 3GHz and 10GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S21>10dB) with a good input impedance matching less than –10dB and a minimum noise figure of 2.9dB over the entire band. The proposed UWB LNA consumed 15.2mW from a 1.8V power supply.

CMOS Ultra-Wideband Low Noise Amplifier Design

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA). The proposed UWB LNA whose bandwidth extends from 2.5 GHz to 16 GHz is designed using a symmetric 3D RF integrated inductor. This UWB LNA has a gain of 11 ± 1.0 dB and a NF less than 3.3 dB. Good input and output impedance matching and good isolation are achieved over the operating frequency band. The proposed UWB LNA is driven from a 1.8 V supply. The UWB LNA is designed and simulated in standard TSMC 0.18 µm CMOS technology process.

Design of an Inductor-Less LNA Using Resistive Feedback Topology for UWB Applications

Low Noise Amplifier (LNA) is one of the essential components in Ultra Wideband (UWB) devices. Conventional LNA suffers from large chip area, high power consumption and inadequate Noise Figure (NF). A compact UWB LNA in the bandwidth of 3.1 to 10.6 GHz is proposed. The design is based on inductor-less configuration using the resistive shunt feedback topology and noise canceling techniques for wideband and high gain characteristics. Designed in 0.18-μm CMOS technology without applying any inductors and capacitors in the core circuit, the chip area is only 0.001 mm² and consumes 16.11 mW of power at 1.5-V supply. The maximum gain is 18.01 dB and the minimum NF noise is 1.324 dB.

A low power and high linearity UWB low noise amplifier (LNA) for 3.1–10.6 GHz wireless applications in 0.13 μm CMOS process

In this paper, a low power ultra-wideband (UWB) CMOS LNA was designed exploiting source inductive degeneration technique operating in the frequency range of 3.1–10.6GHz. In order to achieve low noise figure and high linearity simultaneously, a modified three-stage UWB LNA with inter-stage inductors was proposed. Forward Body-Biased (FBB) technique was used to reduce threshold voltage and power consumption at the first and third stages. The second stage is a push–pull topology exploiting the complementary characteristics of NMOS and PMOS transistors to enhance the linearity performance. The proposed LNA was simulated in standard 0.13μm CMOS process. A gain of 19.5±1.5dB within the entire band was exhibited. The simulated noise figure (NF) was 1–3.9dB within the bandwidth. A maximum simulated third-order input intercept point (IIP3) of 4.56dBm while consuming 4.1mW from a 0.6 power supply was achieved. The simulated input return loss (S11) was less than −5dB from 4.9 to 12.1GHz. The output return loss (S22) was below −10.6dB and S12 was better than −70.6dB.

인덕터 피킹기법을 이용한 초광대역 CMOS 저잡음 증폭기 설계

본 논문에서는 3.1-10.6GHz 초광대역 CMOS 저잡음 증폭기의 새로운 구조를 소개하였다. 제안된 초광대역 저잡음 증폭기는 입력 임피던스 정합에 RC 피드백과LC 필터회로를 사용하여 설계되었다. 이 설계에 전류 재사용 구조는 전력소비를 줄이기 위해 채택되었으며, 인덕터 피킹 기법은 대역폭을 확장하기 위하여 적용되었다. 이 초광대역 저잡음 증폭기의 특성을 <TEX>$0.18-{\mu}m$</TEX> CMOS 공정기술로 시뮬레이션을 수행한 결과는 3.1-10.6GHz 대역 내에서 전력이득은 14-14.9dB, 입력정합은 -10.8dB이하, 평탄도는 0.9dB, 잡음지수는 2.7-3.3dB인 것을 보여준다. 또한, 입력 IP3는 -5dBm이고, 소비전력은 12.5mW이다. In this paper, a new circuit topology of an ultra-wideband (UWB) 3.1-10.6GHz CMOS low noise amplifier is presented. The proposed UWB low noise amplifier is designed utilizing RC feedback and LC filter networks which can provide good input impedance matching. In this design, the current-reused topology is adopted to reduce the power consumption and the inductor-peaking technique is applied for the purpose of bandwidth extension. The performance results of this UWB low noise amplifier simulated in <TEX>$0.18-{\mu}m$</TEX> CMOS process technology exhibit a power gain of 14-14.9dB, an input matching of better than -10.8dB, gain flatness of 0.9dB, and a noise figure of 2.7-3.3dB in the frequency range of 3.1-10.6GHz. In addition, the input IP3 is -5dBm and the power consumption is 12.5mW.

3.1–10.6 GHz ultra-wideband LNA design using dual-resonant broadband matching technique

This paper presents an ultra-wideband low noise amplifier design using the dual-resonant broadband matching technique. The proposed LNA achieves a 10.2dB gain with ±0.9dB gain flatness over a frequency range of 3.1–10.6GHz and a −3-dB bandwidth of 2.4–11.6GHz. The measured noise figure ranges from 3.2 to 4.7dB over 3.1–10.6GHz. At 6.5GHz, the measured IIP3 and input-referred P1dB are +6dBm and −5dBm, respectively. The proposed LNA occupies an active chip area of 0.56mm2 in a TSMC 0.18μm RF-CMOS process and consumes 16mW from a 1.8V supply.

A Low-Power Ultrawideband Low-Noise Amplifier in 0.18 μm CMOS Technology

This paper presents an ultrawideband low-noise amplifier chip using TSMC 0.18&#x2009;<i >&#x3bc;</i>m CMOS technology. We propose a UWB low noise amplifier (LNA) for low-voltage and low-power application. The present UWB LNA leads to a better performance in terms of isolation, chip size, and power consumption for low supply voltage. This UWB LNA is designed based on a current-reused topology, and a simplified RLC circuit is used to achieve the input broadband matching. Output impedance introduces the LC matching method to reduce power consumption. The measured results of the proposed LNA show an average power gain (<i >S</i>₂₁) of 9&#x2009;dB with the 3&#x2009;dB band from 3 to 5.6&#x2009;GHz. The input reflection coefficient (<i>S</i>₁₁) less than &#x2212;9&#x2009;dB is from 3 to 11&#x2009;GHz. The output reflection coefficient (<i>S</i>₂₂) less than &#x2212;8&#x2009;dB is from 3 to 7.5&#x2009;GHz. The noise figure 4.6&#x2013;5.3&#x2009;dB is from 3 to 5.6&#x2009;GHz. Input third-order-intercept point (IIP<sub >3</sub>) of 2&#x2009;dBm is at 5.3&#x2009;GHz. The dc power consumption of this LNA is 9&#x2009;mW under the supply of a 1&#x2009;V supply voltage. The chip size of the CMOS UWB LNA is <svg style="vertical-align:-0.1638pt;width:74.362503px;" id="M1" height="11.125" version="1.1" viewBox="0 0 74.362503 11.125" width="74.362503" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,10.862)"><path id="x31" d="M384 0h-275v27q67 5 81.5 18.5t14.5 68.5v385q0 38 -7.5 47.5t-40.5 10.5l-48 2v24q85 15 178 52v-521q0 -55 14.5 -68.5t82.5 -18.5v-27z" /></g><g transform="matrix(.017,-0,0,-.017,8.222,10.862)"><path id="x2E" d="M113 -12q-24 0 -39.5 16t-15.5 42q0 24 16 40.5t40 16.5t40 -16.5t16 -40.5q0 -26 -16 -42t-41 -16z" /></g><g transform="matrix(.017,-0,0,-.017,12.098,10.862)"><path id="x30" d="M241 635q53 0 94 -28.5t63.5 -76t33.5 -102.5t11 -116q0 -58 -11 -112.5t-34 -103.5t-63.5 -78.5t-94.5 -29.5t-95 28t-64.5 75t-34.5 102.5t-11 118.5q0 58 11.5 112.5t34.5 103t64.5 78t95.5 29.5zM238 602q-32 0 -55.5 -25t-35.5 -68t-17.5 -91t-5.5 -105&#xA;q0 -76 10 -138.5t37 -107.5t69 -45q32 0 55.5 25t35.5 68.5t17.5 91.5t5.5 105t-5.5 105.5t-18 92t-36 68t-56.5 24.5z" /></g><g transform="matrix(.017,-0,0,-.017,20.257,10.862)"><path id="x33" d="M285 378v-2q65 -13 102 -54.5t37 -97.5q0 -57 -30.5 -104.5t-74 -75t-85.5 -42t-72 -14.5q-31 0 -59.5 11t-40.5 23q-19 18 -16 36q1 16 23 33q13 10 24 0q58 -51 124 -51q55 0 88 40t33 112q0 64 -39 96.5t-88 32.5q-29 0 -64 -11l-6 29q77 25 118 57.5t41 84.5&#xA;q0 45 -26.5 69.5t-68.5 24.5q-67 0 -120 -79l-20 20l43 63q51 56 127 56h1q66 0 107 -37t41 -95q0 -42 -31 -71q-22 -23 -68 -54z" /></g><g transform="matrix(.017,-0,0,-.017,32.19,10.862)"><path id="xD7" d="M528 54l-36 -38l-198 201l-198 -201l-36 38l197 200l-197 201l36 38l198 -202l198 202l36 -38l-197 -201z" /></g><g transform="matrix(.017,-0,0,-.017,45.942,10.862)"><use xlink:href="#x30"/></g><g transform="matrix(.017,-0,0,-.017,54.102,10.862)"><use xlink:href="#x2E"/></g><g transform="matrix(.017,-0,0,-.017,57.977,10.862)"><path id="x37" d="M447 623l8 -12l-283 -613l-74 -10l-7 11q174 283 297 551h-216q-48 0 -62.5 -12t-33.5 -63h-29q10 60 18 148h382z" /></g><g transform="matrix(.017,-0,0,-.017,66.137,10.862)"><path id="x38" d="M249 635q70 0 116 -43t46 -105q0 -46 -28 -80q-22 -25 -80 -64q62 -35 97 -75t35 -99q0 -81 -63 -131t-135 -50q-83 0 -137.5 45.5t-54.5 123.5q0 52 45 95q29 28 89 64q-109 62 -109 155q0 66 50.5 115t128.5 49zM238 603q-42 0 -67.5 -31t-25.5 -72q0 -50 32.5 -79.5&#xA;t98.5 -62.5q61 48 61 124q0 59 -29.5 90t-69.5 31zM248 20q46 0 76.5 33.5t30.5 89.5q0 50 -39 85.5t-110 71.5q-81 -54 -81 -137q0 -67 35.5 -105t87.5 -38z" /></g> </svg>&#x2009;mm<sup >2</sup> in total.

Out-Band Interference Rejection in UWB LNA Receiver Using Coupled Inductors in Front End LNA

In this paper, an ultra wide band (UWB) low noise amplifier (LNA) circuit with a new input stage is proposed. In this scheme, a combination of coupled inductors in the input stage is utilized. The input stage is able to easily reject out-band interference. This input stage is applied in an LNA with 0.18 μm technology. The LNA has a peak gain of 21.72 dB in 3.1-10.6 GHz frequency band while showing a minimum noise figure of 1.85 dB in the mentioned frequency band. This circuit rejects 15.2 dB out-band interference, while power consumption of the UWB LNA core is 11.8 mW DC which is supplied from a 1.8 V power supply. s11 is less than -10.3 dB over the entire bandwidth since the worst value of IIP3 over the entire bandwidth is -13 dBm, which occurs at the frequency of 10.6 GHz.

A 3–5 GHz Current-Reuse $g_{m}$-Boosted CG LNA for Ultrawideband in 130 nm CMOS

This paper presents a low-power CMOS transconductance “ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> ” boosted common gate (CG) ultrawideband (UWB) low noise amplifier (LNA) architecture, operating in the 3-5 GHz range, employing current-reuse technique. This proposed UWB CG LNA utilizes a common source (CS) amplifier as the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gm</i> -boosting stage which shares the bias current with the CG amplifying stage. A detailed mathematical analysis of the LNA is carried out and the different design tradeoffs are analyzed. The LNA circuit was designed and fabricated using the 130-nm IBM CMOS process and it achieved input return loss (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) and output return loss (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">22</sub> ) variations of respectively - 8.4 to - 40 dB and - 14 to - 15 dB within the pass-band. The LNA exhibits almost flat forward power gain (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) of 13 dB and a reverse isolation (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sub> ) variation of -55 dB to -40 dB, along with a noise figure (NF) ranging between 3.5 and 4.5 dB. The complete circuit (with output buffer) draws only 3.4 mW from a 1 V supply voltage.

Ultra-Wideband Low-Noise Amplifier

Abstract Ultra-Wideband (UWB) Low-Noise Amplifier (LNA) is an essential part of the digital TV and UWB signal processor, but what makes it hard to design is the comprehensive consideration of bandwidth, noise and gain control performance. A new solution of high performance amplifier with low-noise, UWB and direct current (DC) is presented (Fig.1), which is composed of a precision pre-amplifier with AD797, a stepped gain controller with VCA810 and a digital potentiometer, an eight-order Bessel low-pass filter with LC network, a zero-drift corrector with the digital compensation method. The test results (Tab 1-3 & Fig.6) show that the gain of amplifier can be adjusted from 0 to 80 dB by step, the fluctuation of the pass band from DC to 10 MHz is less than 0.87 dB, stop-band attenuation reaches -42 dB/2fc, the equivalent input noise voltage is less than 7.2 μVrms. This design successfully solves some high challenging contradictions, such as ultra-wideband and low-noise, stop-band attenuation and pass-band fluctuation, precise gain control and DC zero-drift correction.

3.2–9.7 GHz ultra-wideband low-noise amplifier with excellent stop-band rejection

A low-power 3.2–9.7 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent stop-band rejection by 0.18 µm CMOS technology is demonstrated. High stop-band rejection is achieved by using a passive bandpass filter (BP-filter) with three finite transmission zeros (in the input terminal), one of which (ωz1=0.9 GHz) is in the low-frequency stop-band and the other two (ωz3 and ωz5) are in the high-frequency stop-band. In addition, an active notch filter is used in the output terminal to introduce another low-frequency stop-band transmission zero (ωz2) at 2.4 GHz. The LNA consumes 4.68 mW and achieves S11 of −10 to −39.5 dB, S21 of 9.3±1.5 dB, and an average NF of 6 dB over the 3.2–9.7 GHz band. The measured stop-band rejection is better than 21.6 dB for frequencies DC–2.5 and 11.2–20 GHz.

A low power UWB low noise amplifier using current reused and feedback techniques

AbstractThis letter presents a full band low power low noise amplifier design in 0.18‐μm complementary metal‐oxide‐semiconductor FET (CMOS) technology.The proposed circuit adopts current reused technique to achieve low power consumption, and shunt resistive feedback for wide‐band operation. An excellent wide and flat gain, low noise figure, are achieved by composes of these techniques. The implemented ultra‐wideband (UWB) low noise amplifier (LNA) exhibits a flat gain of 18 dB with total power consumption of 5.2 mA from 1.8 V power supply. The noise figure is 3.1 dB within the entire bandwidth. The input and output return loss is less than −10 dB in the specified bandwidth. The proposed technique exhibits 0.8 dBm of IIP3. The active die area of UWB LNA occupies 0.72 mm2. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett, 54:471–474, 2012; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.26550

A High Thermal Stability 3-10 GHz Low Noise Amplifier Using Current-reused Schematic with 0.5 ¼m pHEMT Technique

The objective of this article was to investigate if the ultra-wideband (UWB) low-noise amplifier (LNA) was modeled by utilizing a two-stage cascade circuit schematic, associated with the DC current-reused technique, which could improve the low power consumption in the 3.1–10.6 GHz frequency. The proposed UWB LNA amplifier was implemented with both the co-planer waveguide layout and 0.5-¼m GaAs Enhancement-mode pHEMT technology. Based on these technologies, this proposed UWB LNA, for which the chip size was shown to be 0.917 mm×0.816 mm, presented a flatness gain 3-dB bandwidth of 3.1-10.6 GHz, an excellent noise figure of 2.26–3.36 dB, a maximum power gain of 15.2 dB, and a power consumption of 17.7 mW, at 3 V power supply, respectively. Furthermore, the proposed UWB LNA was performed in the temperature stability measurement, for which stable characterizations of the S-parameters were obtained. Based on our experimental results, the low noise amplifier could obtain a wider band-width, low power consumption, and high flatness of gain in the 3.1–10.6 GHz frequency. Finally, the overall LNA characterization exhibited an ultra-wide bandwidth and low noise characterization, which illustrated that the proposed UWB LNA had a circuit compact size and exhibited favorable 3–10 GHz microwave characteristics.

A 3.1~10.6 Ghz Ultra-Wideband SiGe Low Noise Amplifier with Current-Reused Technique

A 3.1 ~ 10.6 GHz Ultra-Wideband SiGe Low Noise Amplifier (LNA) is proposed. This low noise amplifier utilizes a current-reused technique to increase the gain and extend the bandwidth. We have a detailed analysis for the input matching, noise figure, gain and other features. The LNA was designed with the TSMC 0.35µm bipolar silicon-germanium (SiGe) processes. Simulation results show that the input reflection coefficient is less than-9dB, the output reflection coefficient is less than-10dB, the maximum power gain of 17 dB and the minimum noise factor (NF) of 2.35dB. The total power consumption is 6.2 mW with 2.5V power supply.

A 78 $\sim$ 102 GHz Front-End Receiver in 90 nm CMOS Technology

In this letter, a 78 ~ 102 GHz front-end receiver designed in 90 nm CMOS technology is presented. It consists of an ultra-wideband low-noise amplifier, a subharmonic mixer, and an IF buffer. This receiver has a peak gain of 11.8 dB at 94 GHz with the noise figure of 13.4 dB. The measured input-referred 1 dB compression point is -14.5 dBm and the total power dissipation is 18.6 mW. The chip size is 680 × 1020 μm2.

A 0.9-V, 7-mW UWB LNA for 3.1–10.6-GHz wireless applications in 0.18-[formula omitted] CMOS technology

This paper presents a low-voltage and low-power CMOS low noise amplifier (LNA) for ultra-wideband (UWB) wireless applications. A cascade stage topology based on common source amplifier has been proposed to reduce the supply voltage of the proposed LNA. In addition, a high-pass filtering network is chosen instead of a Chebyshev band pass structure to simultaneously perform the wideband input matching and to improve the noise figure over the desired band. Using a 0.18μm CMOS process, the proposed LNA exhibit a state of the art performance consuming only 7mW from a 0.9V supply voltage. Post-layout simulation results show a power gain S21 of 13.5dB with gain ripple of ±1.5dB, in the frequency range of 3.1–10.6GHz. The noise figure is below 4.6dB with a minimum of 2.7dB at 4.5GHz. The input and output return losses S11 and S22 are better than −9dB and −15dB, respectively. The highest value of IP3 is −8dBm obtained at 5GHz. The active silicon area occupied by the UWB–LNA is only 0.59mm2.

A 0.18 μm CMOS low noise amplifier using a current reuse technique for 3.1–10.6 GHz UWB receivers

A new, low complexity, ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented. The ultra-wideband LNA consists of only two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration technique is used to attain a wideband input matching and low noise figure. A common source amplifier with an inductive peaking technique as the second stage achieves high flat gain and wide −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, and a high reverse isolation of −45 dB, and good input/output return losses are better than −10 dB in the frequency range of 3.1−10.6 GHz. An excellent noise figure (NF) of 2.8−4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area, including testing pads, is only 0.8 × 0.9 mm2.