Ultra-wideband Low Noise Amplifier Research Articles

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1–10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm 2, including all pads. The measured input return loss is kept below −11 dB, and the output return loss is −8 dB, from 3.1 to 10.6 GHz.

Design of 3.1–10.6 GHz ultra-wideband CMOS low noise amplifier with current reuse technique

A new low complexity ultra-wideband 3.1–10.6 GHz low noise amplifier (LNA), designed in a chartered 0.18 μm RFCMOS technology, is presented in this paper. The ultra-wideband LNA only consists of two simple amplifiers with an inter-stage inductor connected. The first stage utilizing a resistive current reuse and dual inductive degeneration techniques is used to attain a wideband input matching and low noise figure. A common source amplifier with inductive peaking technique as the second stage achieves high flat gain and wide the −3 dB bandwidth of the overall amplifier simultaneously. The implemented ultra-wideband LNA presents a maximum power gain of 15.6 dB, a high reverse isolation of −45 dB and a good input/output return losses are better than −10 dB in the frequency range of 3.1–10.6 GHz. An excellent noise figure (NF) of 2.8–4.7 dB was obtained in the required band with a power dissipation of 14.1 mW under a supply voltage of 1.5 V. An input-referred third-order intercept point (IIP3) is −7.1 dBm at 6 GHz. The chip area including testing pads is only 0.8 mm × 0.9 mm.

Design of a 1~10 GHz High Gain Current Reused Low Noise Amplifier in 0.18 ㎛ CMOS Technology

In this paper, we propose a high gain, current reused ultra wideband (UWB) low noise amplifier (LNA) that uses TSMC 0.18 <TEX>${\mu}m$</TEX> CMOS technology. To satisfy the wide input matching and high voltage gain requirements with low power consumption, a resistive current reused technique is utilized in the first stage. A <TEX>${\pi}$</TEX>-type LC network is adopted in the second stage to achieve sufficient gain over the entire frequency band. The proposed UWB LNA has a voltage gain of 12.9~18.1 dB and a noise figure (NF) of 4.05~6.21 dB over the frequency band of interest (1~10 GHz). The total power consumption of the proposed UWB LNA is 10.1 mW from a 1.4 V supply voltage, and the chip area is <TEX>$0.95{\times}0.9$</TEX> mm.

A miniature low-power ultra-wideband low noise amplifier in 0.18 μm CMOS

A 0.18-μm CMOS low-noise amplifier (LNA) operating over the entire ultra-wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of −8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from −8 to −1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm2 without RF and DC pads. The design uses only two on-chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.

3 - 10 GHz Ultra-Wideband Low-Noise Amplifier Using Inductive-Series Peaking Technique with Cascode Common-Source Circuit

The objective of this paper is to investigate a ultra-wideband (UWB) low noise amplifier (LNA) by utilizing a two-stage cascade circuit schematic associated with inductive-series peaking technique, which can improve the bandwidth in the 3-10 GHz microwave monolithic integrated circuit (MMIC). The proposed UWB LNA amplifier was implemented with both co-planer waveguide (CPW) layout and 0.15-μm GaAs D-mode pHEMT technology. Based on those technologies, this proposed UWB LNA with a chip size of 1.5 mm x 1.4 mm, obtained a flatness gain 3-dB bandwidth of 4 - 8 GHz, the constant gain of 4 dB, noise figure lower than 5 dB, and the return loss better than –8.5 dB. Based on our experimental results, the low noise amplifier using the inductive-series peaking technique can obtain a wider bandwidth, low power consumption and high flatness of gain in the 3 - 10 GHz. Finally, the overall LNA characterization exhibits ultra-wide bandwidth and low noise characterization, which illustrates that the proposed UWB LNA has a compact size and favorable RF characteristics. This UWB LNA circuit demonstrated the high RF characterization and could provide for the low noise micro-wave circuit applications.

Power-Constrained Third-Order Active Notch Filter Applied in IR-LNA for UWB Standards

This brief proposes a third-order active notch filter for an interferer-rejection (IR) ultrawideband low-noise amplifier (LNA) in a 0.18-μm complementary metal-oxide-semiconductor process. The design formulas are derived by considering the minimum power dissipation for the active notch filter that provides proper selections of the device size, the bias conditions, and the values of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> resonator. The active notch filter was then incorporated into a wideband common-gate LNA as an IR-LNA. The measurements show that the IR-LNA achieves a maximum gain of 14.7 dB, a minimum noise figure of 5.3 dB, an IR ratio of 35.7 dB, and an input third-order intercept point of -2.5 dBm at a 16-mW power dissipation, while the active notch filter rejects the interfering signal at 5.8 GHz. The chip area is 0.51 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , including testing pads.

0.99 mW 3–10 GHz common-gate CMOS UWB LNA using T-match input network and self-body-bias technique

A low-power 3–10 GHz common-gate CMOS ultra-wideband (UWB) low-noise amplifier (LNA) using a T-match input network and the self-body-bias technique is demonstrated. Wideband input impedance matching was achieved by using the proposed T-match input network to improve the input matching at low frequencies. A low supply voltage of 1.1 V (for two VDS drops) was achieved by using the self-body-bias technique to reduce the threshold voltage (Vth) of the transistors, which leads to a low power consumption (PD). At VG=0.77 V, the LNA consumed 2.15 mW and achieved S11 of −10.4 to −35.5 dB, S21 of 10.4 dB, and an average NF of 4.9 dB over the 3–10 GHz band of interest. At VG=0.63 V, the LNA consumed 0.99 mW and achieved S11 of −10.7 to −35.8 dB, S21 of 7.9 dB and an average NF of 6 dB. Both are the lowest PD ever reported for an UWB CMOS LNA with bandwidth greater than 6 GHz.

Design and analysis of a compact ultra‐wideband CMOS low‐noise amplifier

AbstractIn this letter, we proposed a low power, high gain, compact ultra‐wideband (UWB) low noise amplifier (LNA) using TSMC 0.18‐μm CMOS technology.To satisfy the wide input matching and high voltage gain requirements with low power consumption, a resistive current reused technique is utilized. The proposed UWB LNA has a voltage gain of 10.4–15.5 dB and a noise figure (NF) of 3.3–4.5 dB over the frequency band of interest (1–8 GHz). The total power consumption of the proposed UWB LNA is 10.4 mW from a 1.4 V supply voltage, and the chip area is 0.8 mm × 0.5 mm. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:345–348, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25747

A 2.76‐mW, 3‐ to 10‐GHz ultrawideband LNA using 0.18‐μm CMOS technology

AbstractA low‐power (2.76 mW) common‐gate (CG) low‐noise amplifier (LNA) for ultrawideband (UWB) systems using standard 0.18 μm CMOS technology is demonstrated.Instead of the traditional single parallel inductor (LS1 only), we propose a new matching network consisting of a series LS1–RS1 in series with a parallel LS2–RS2 to enhance the input matching bandwidth. Flat and high S21 was achieved by using the connecting inductor LC and the peaking inductor LD2 to compensate the gain loss at medium frequency and high frequency, respectively. In addition, for suitable values of LC and LD2, flat and low noise figure (NF; i.e., a nearly critically damped Q‐factor for the second‐order NF frequency response) can also be achieved. Over the 3–10 GHz band of interest, the LNA achieved S21 of 10.1 ± 1.7 dB, minimum NF of 3.9 dB (at 4 GHz) and an average NF of 4.6 dB. The power dissipation was 2.76 mW, and the corresponding figure of merit was 4.3. Both are of the best results ever reported for a CMOS UWB LNA. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:94–97, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25667

Novel analysis and optimization of gm-boosted common-gate UWB LNA

This paper focuses on the design optimization of gm-boosted common gate (CG) CMOS low-noise amplifier (LNA) for ultra-wideband (UWB) wireless technology. In this regard, a detailed novel analysis of the UWB gm-boosted CG amplifier topology is presented, which includes the finite gds (=1/reds) effects. For UWB systems, signal-to-noise ratio (SNR) can be defined as the matched filter bound (MFB). Using this definition, the noise performance of the UWB CG LNA in the presence of the gm-boosting gain and the input noise-matching network are analyzed. It is found that the optimal noise factor of the UWB LNA collapses to the published narrowband gm-boosted CG LNA noise factor when an assumption of narrowband is applied. It is also proved that the noise performance of the gm-boosted UWB CG LNA is independent of the bandwidth of the input UWB signal. A new technique is presented for the design of optimal noise-matching network using passive components at the input of the UWB CG LNA. In this regard, role of the gm-boosting stage and its effect on the SNR and the gain of the overall system are analyzed, and, in addition, its non-idealities are simulated in detail.

A 1–25 GHz GaN HEMT MMIC Low-Noise Amplifier

This letter presents an ultra-wideband low noise amplifier (LNA) using gallium-nitride (GaN) high-electron mobility transistors (HEMT) technology. A -3 dB bandwidth of 1-25 GHz with 13 dB peak power gain is achieved using a modified resistive-feedback topology. To obtain such a wide bandwidth, several bandwidth enhancement techniques are utilized. An inductor connected to the source of the input transistor ensures good input matching (|S11| <; -9 dB) across the entire bandwidth. The shunt feedback loop and the inductive source degeneration minimize all the required inductor values. This GaN HEMT LNA is believed to have the widest bandwidth among all GaN HEMT monolithic microwave integrated circuit (MMIC) LNAs reported to date. With 3.3 dB minimum noise figure (F), 33.5 dBm maximum output-referred third-order intercept point (OIP3), 20 dBm maximum output-referred 1 dB compression point (Output P1 dB), this MMIC amplifier is comparable in performance to distributed amplifiers (DAs) but with significantly lower power consumption and smaller area.

A Compact 0.1&amp;#x2013;14-GHz Ultra-Wideband Low-Noise Amplifier in 0.13-&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\mu{\hbox{m}}$&lt;/tex&gt; &lt;/formula&gt; CMOS

A compact ultra-wideband low-noise amplifier (LNA) with a 12.4-dB maximum gain, a 2.7-dB minimum noise figure (NF), and a bandwidth over 0.1-14 GHz is realized in a 0.13-μm CMOS technology. The circuit is basically an inductorless configuration using the resistive-feedback and current-reuse techniques for wideband and high-gain characteristics. It was found that a small inductor of only 0.4 nH can greatly improve the circuit performance, which enhances the bandwidth by 23%, and reduces the NF by 0.94 dB (at 10.6 GHz), while only consuming an additional area of 80 × 80 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The LNA only occupies a core area of 0.031 mm , and consumes 14.4 mW from a 1.8-V supply.

An Area-Efficient Multistage 3.0- to 8.5-GHz CMOS UWB LNA Using Tunable Active Inductors

An area-efficient multistage 3.0- to 8.5-GHz ultrawideband low-noise amplifier (LNA) utilizing tunable active inductors (AIs) is presented. The AI includes a negative impedance circuit (NIC) consisting of a pair of cross-coupled NMOS transistors and is tuned to vary the gain and bandwidth (BW) of the amplifier. Fabricated in a 90-nm digital CMOS process, the proposed fully on-chip LNA occupies a core chip area of only 0.022 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measurement results show a power gain S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> of 16.0 dB, a noise figure of 3.1-4.4 dB, and an input return loss S11 of less than -10.5 dB over the 3-dB BW of 3.0-8.5 GHz. Tuning the AIs allows one to increase the gain above 18.0 dB and to extend the BW over 9.4 GHz. The LNA consumes 16.0 mW from a power supply of 1.2 V.

Parallel-RC Feedback Low-Noise Amplifier for UWB Applications

A two-stage 3.1- to 10.6-GHz ultrawideband CMOS low-noise amplifier (LNA) is presented. In our design, a parallel resistance-capacitance shunt feedback with a source inductance is proposed to obtain broadband input matching and to reduce the noise level effectively; furthermore, a parallel inductance-capacitance network at drain is drawn to further suppress the noise, and a very low noise level is achieved. The proposed LNA is implemented by the Taiwan Semiconductor Manufacturing Company 0.18-μm CMOS technology. Measured results show that the noise figure is 2.5-4.7 dB from 3.1 to 10.6 GHz, which may be the best result among previous reports in the 0.18-μm CMOS 3.1- to 10.6-GHz ultrawideband LNA. The power gain is 10.9-13.9 dB from 3.1 to 10.6 GHz. The input return loss is below -9.4 dB from 3.1 to 15 GHz. It consumes 14.4 mW from a 1.4-V supply voltage and occupies an area of only 0.46 mm2.

Design and implementation of a 1–5 GHz UWB low noise amplifier in 0.18 μm CMOS

This paper presents a compact two-stage ultra-wideband low-noise amplifier (LNA). A common-gate topology is adopted for the input stage to achieve wideband input matching, while a cascode stage is used as the second stage to provide power gain at high frequencies. A low power consumption and a small chip area are obtained by optimizing the performance of the LNA with tight constraint on biasing current and reducing the number of inductors to two. The LNA has been fabricated in a standard 0.18 μm CMOS technology for experimental verification. The LNA achieves a power gain of 11---13.7 dB and a noise figure of 5.0---6.5 dB in the frequency band 1-5 GHz. The measured third order (two-tone) input intercept point (IIP3) is ?9.8 dBm at 4 GHz. The LNA consumes 9 mW with a 1.8 V supply, and it occupies an area of 0.78 mm2.

A low-power 3.1–10.6 GHz ultra-wideband CMOS low-noise amplifier with common-gate input stage

A low-power ultra-wideband (UWB) low-noise amplifier (LNA) is proposed exploiting a current-reused technique operating in the frequency range of 3.1–10.6 GHz. The technique stacks two-stage amplifiers in dc, thereby reusing the dc current and saving the power consumption significantly. With the common-gate configuration at the input stage, broad-band input matching is obtained with less than −5 dB input reflection coefficient in 3–10 GHz frequency range. Fabricated with 0.18-μm RFCMOS technology, the proposed LNA achieves about 10 dB power gain and noise figure (NF) of 4.6–7.8 dB within 3 dB bandwidth of 2.2–9.7 GHz. The LNA core excluding the buffer consumes only 2.9 mW from a 1.8 V supply voltage. The input third order intercept point (IIP3) of the LNA is −8.5 dBm at 6 GHz.

A 4 mW 3–5 GHz current reuse gm-boosted short channel common-gate CMOS UWB LNA

A novel architecture is presented to optimize the noise performance and the power consumption of the transconductance `gm' boosted common-gate (CG) ultrawideband (UWB) low-noise amplifier (LNA), operating in the 3---5 GHz range, by employing current reuse technique. This proposed CG LNA utilizes a common source (CS) amplifier as the gm-boosting stage and the bias current is shared between the gm-boosting stage and the CG amplifying stage. The LNA circuit also utilizes the short channel conductance gds in conjunction with an LC T-network to further reduce the noise figure (NF). The proposed LNA architecture has been fabricated using the 130 nm IBM CMOS process. The LNA achieved input return loss (S11) of ?8 to ?10 dB, and, output return loss (S22) of ?12 to ?14 dB, respectively. The LNA exhibits almost flat forward voltage gain (S21) of 13 dB, and reverse isolation (S12) of ?62 to ?49 dB, with a NF ranging between 3.8 and 4.6 dB. The measurements indicate an input-referred third order intercept point (IIP3) of ?6.1 dBm and an input-referred 1-dB compression point (ICP1dB) of ?15.4 dBm. The complete chip draws 4 mW of DC power from a 1.2 V supply.

Low-Noise Amplifier Design With Dual Reactive Feedback for Broadband Simultaneous Noise and Impedance Matching

The simultaneous noise and impedance matching (SNIM) condition for a common-source amplifier is analyzed. Transistor noise parameters are derived based on the more complete hybrid-¿ model, and the dominant factors jeopardizing SNIM are identified. Strategies for narrowband and broadband SNIM (BSNIM) are derived accordingly. A dual reactive feedback circuit along with an LC-ladder matching network is proposed to achieve the BSNIM. It includes a capacitive and an inductive feedback, where the former utilizes the transistor parasitic gate-to-drain capacitance and the latter is formed by transformer coupling. This circuit topology has been validated in 0.18- and 0.13- ¿m CMOS technologies for a 3-11-GHz ultra-wideband (UWB) and a 2.4-5.4-GHz multistandard application, respectively. The 3-11-GHz UWB low-noise amplifier is detailed as a design example.

Analysis and Design of Two Low-Power Ultra-Wideband CMOS Low-Noise Amplifiers With Out-Band Rejection

Two 3-5-GHz low-power ultra-wideband (UWB) low-noise amplifiers (LNAs) with out-band rejection function using 0.18- ¿m CMOS technology are presented. Due to the Federal Communications Commission's stringent power-emission limitation at the transmitter, the received signal power in the UWB system is smaller than those of the close narrowband interferers such as the IEEE 802.11 a/b/g wireless local area network, and the 1.8-GHz digital cellular service/global system for mobile communications. Therefore, we proposed a wideband input network with out-band rejection capability to suppress the out-band properties for our first UWB LNA. Moreover, a feedback structure and dual-band notch filter with low-power active inductors will further attenuate the out-band interferers without deteriorating the input matching bandwidth in the second UWB LNA. The 55/48/45 dB maximum rejections at 1.8/2.4/5.2 GHz, a power gain of 15 dB, and 3.5-dB minimum noise figure can be measured while consuming a dc power of only 5 mW.

Analysis and Design of a CMOS UWB LNA With Dual-$RLC$-Branch Wideband Input Matching Network

A wideband low-noise amplifier (LNA) based on the current-reused cascade configuration is proposed. The wideband input-impedance matching was achieved by taking advantage of the resistive shunt-shunt feedback in conjunction with a parallel LC load to make the input network equivalent to two parallel RLC-branches, i.e., a second-order wideband bandpass filter. Besides, both the inductive series- and shunt-peaking techniques are used for bandwidth extension. Theoretical analysis shows that both the frequency response of input matching and noise figure (NF) can be described by second-order functions with quality factors as parameters. The CMOS ultra-wideband LNA dissipates 10.34-mW power and achieves <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> below -8.6 dB, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">22</sub> below -10 dB, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sub> below -26 dB, flat <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> of 12.26 ± 0.63 dB, and flat NF of 4.24 ± 0.5 dB over the 3.1-10.6-GHz band of interest. Besides, good phase linearity property (group-delay variation is only ±22 ps across the whole band) is also achieved. The analytical, simulated, and measured results agree well with one another.