ULSI Technology Research Articles

STEM Energy-Dispersive X-ray Spectroscopy for Quantitative Compositional Metrology in ULSI Technology

STEM Energy-Dispersive X-ray Spectroscopy for Quantitative Compositional Metrology in ULSI Technology

Effect of UV, IR and microwave radiation on Tween-80 porogen based low-k films

Low dielectric constant (low-k) films due to their potential application as an inter-layer dielectric (ILD) attracted significant attention of researchers and scientists. Porous low-k films like xerogel, aerogel, porogen based and hybrid films are extensively investigated as they have dielectric constant value less than that of SiO2. Considering the advantages of porous low-k films, current investigation focused onto the study of porogen based porous low-k films. To obtain low-k films, solgel based spin-on technique is used. Incorporation of Tween-80 porogen in deposited low-k films is confirmed through the presence of –CH2-CH3 group around 2856–2916 cm−1 in FTIR spectra. Removal of porogen material from film matrix was done by using radiation exposure of samples and is confirmed through FTIR analysis. Refractive indices (RI) of deposited porogen based films treated with UV, IR and microwave radiations are observed to be 1.28, 1.29 and 1.33, respectively. Further, density of IR, UV and microwave radiation is calculated from RI, and is observed to be decreased for UV radiation up to 1.38 gm/cm3. Dielectric constant value k = 2.7 was achieved for UV treated samples. Investigation suggests that low-k films having lower k value may have potential applications as ILD for ULSI technology.

Performance Analysis of CMOS Technology

The project titled “Performance Evaluation of CMOS Technology” is a research conducted to provide students with guidelines about what to invest their time in the field of VLSI & ULSI technology and enlighten them about various parameters of Scaling of CMOS technology which is the most used IC technology in the world. This report also studies the range of scaling of MOSFET and its limits. The performance of a device relies highly on the performance of the IC and Transistors used in its circuit hardware. CMOS which is the abbreviation of Complementary Metal Oxide Semiconductor is a technology used to design Integrated Circuits. The Complementary prefix to MOS that refers to MOSFET signifies the use of complementary semiconductors that is NMOS and PMOS. These two MOS technologies work together to form a wide array of gates and Integrated Circuits. This research provides students various results on the unreliability of Student Version Simulation software in designing new generation hardware and how power dynamics of highly scaled technology cannot be verified using such tools.

Review on modeling and application of chemical mechanical polishing

Abstract With the development of integrated circuit technology, especially after entering the sub-micron process, the reduction of critical dimensions and the realization of high-density devices, the flatness between integrated circuit material layers is becoming more and more critical. Because conventional mechanical polishing methods inevitably produce scratches of the same size as the device in metal or even dielectric layers, resulting in depth of field and focus problems in lithography. The first planarization technique to achieve application is spin on glass (SOG) technology. However, this technology will not only introduce new material layers, but will also fail to achieve the global flattening required by VLSI and ULSI technologies. Moreover, the process instability and uniformity during spin coating do not meet the high flatness requirements of the wafer surface. Also, while some techniques such as reverse etching and glass reflow can achieve submicron level regional planarization. After the critical dimension reaches 0.35 microns (sub-micron process), the above methods cannot meet the requirements of lithography and interconnect fabrication. In the 1980s, IBM first introduced the chemical mechanical polishing (CMP) technology used to manufacture precision optical instruments into its DRAM manufacturing [1]. With the development of technology nodes and critical dimensions, CMP technology has been widely used in the Front End Of Line (FEOL) and Back End Of Line (BEOL) processes [2]. Since the invention of chemical mechanical polishing, scientists have not stopped studying its internal mechanism. From the earliest Preston Formula (1927) to today’s wafer scale, chip scale, polishing pad contact, polishing pad - abrasive - wafer contact and material removal models, there are five different scale models from macro to the micro [3]. Many research methods, such as contact mechanics, multiphase flow kinetics, chemical reaction kinetics, molecular dynamics, etc., have been applied to explain the principles of chemical mechanical polishing to establish models. This paper mainly introduces and summarizes the different models of chemical mechanical polishing technology. The various application scenarios and advantages and dis-advantages of the model are discussed, and the development of modeling technology is introduced.

A Fast-Efficient parallel processing algorithm for straight line detection

<p>This work presents a novel method for detecting straight lines in an image at a very high speed with optimum number of processors and their functionalities. The method can be used to extract straight lines directly from an image without noise removal and pre-processing. First the square image is converted to a binary edge image using a parallel edge detection mechanism. The parallel edge detection mechanism used in this work is capable of producing edge image within a short time. Then the binary square image is transferred to a system having large number of Processing Elements (PEs). A PE has only limited jobs such as pixel scanning, compare line length with nearby PEs and transmit data to the Main Control Unit (MCU). The MCU collects data from all PEs and evaluates straight lines. Even if the number of PEs is high, it is comparatively very much less than the parallel Hough Transform method and practically implementable using recent ULSI technologies.</p>

Low power-high speed performance of 8T static RAM cell within GaN TFET, FinFET, and GNRFET technologies – A review

Recent ULSI technology development emphasizes both silicon and graphene-based devices and system performance in terms of their low power and high switching speed. With Moore’s law scaling having reached the limits of physics due to ballistic effects, efforts are moving towards nano scale materials and devices such as TFETs and GNRFETs. Still, recent developments with 7 nm lithography-based silicon devices have cited exciting results. The successful development of FinFET devices in integrated systems has been a breakthrough for the semiconductor industry. Research efforts were emphasized for new nanoscale materials such as Graphene, GaN, and Carbon nanotubes, as alternative devices for ULSI integrated system design. This paper provides a cumulative review for these three nanoscale devices: FinFET, TFET, and GNRFET. The study focuses on an 8T SRAM cell as geared towards low power and high-speed features that are suitable for high speed computers, wireless communications, and medical devices. The study covers device theory, models, and simulation. The study has showed evidence that the power consumption for both TFET and GNRFET -based systems features superior low power performance of a ratio 1:0.24 as taken for the Static T Cell for 20 nm scale devices. The practical model of the FinFET is verified and used by industry, while the practical model of both TFET and GNRFET are still in the prototype stage.

ULSI and Thin Film Semiconductor Technologies: Evolution of Industry and Research Linked to Higher Education in France

This paper discusses the evolution since the early 1980s of microelectronics applied to integrated circuits (ULSI) and large surface electronics (TFT) in France, both in industry and in academic institutions. This strategy is the result of the French government's policy to support the development of industry and higher education. The objective was to provide industry with future technicians, engineers, masters and doctors with the knowledge, know-how and capacity to develop this field as in advanced countries. More recently, a new government plan has been initiated to develop connected objects and the Internet of Things, mandatory for the emerging digital society. These correspond to the combination of ULSI and TFT technologies. After a synthetic presentation of the evolution of the industrial and academic environment, the paper highlights the evolution of the two main technologies as well as the strategy developed by the French educational community based on innovation and enabling it to bring know-how and skills in this field.

Improved Current Drivability for Sub-20-nm N-FinFETs by Ge Pre-Amorphization in Contact With Reverse Retrograde Profile

Prior to contact silicide formation, multiple Ge pre-amorphization implantation (PAI) with reverse retrograde Ge profile was investigated for sub-20-nm FinFETs. Compared with conventional single PAI, N-FinFETs from the new PAI scheme exhibit enhanced drive current by 12%, which can be attributed to decreased total series resistance ( ${\mathrm {R}}_{\mathrm {{{Total}}}}$ ) by 15% and enhanced peak electron mobility by 8%. The former arises from reduced Schottky barrier height and better crystallinity of C49/C54 TiSi2, while the latter is resulted from higher tensile strain in the channel induced by TiSi2 with more Ge incorporation. Furthermore, ring oscillator for the new PAI scheme shows better circuit performance as compared with conventional scheme in terms of 6% increase in output frequency. The newly developed PAI process is fully compatible with the incumbent ULSI technology and can be extended to sub-10-nm FinFETs.

Fermi level pinning characterisation on ammonium fluoride-treated surfaces of silicon by energy-filtered doping contrast in the scanning electron microscope.

Two-dimensional dopant profiling using the secondary electron (SE) signal in the scanning electron microscope (SEM) is a technique gaining impulse for its ability to enable rapid and contactless low-cost diagnostics for integrated device manufacturing. The basis is doping contrast from electrical p-n junctions, which can be influenced by wet-chemical processing methods typically adopted in ULSI technology. This paper describes the results of doping contrast studies by energy-filtering in the SEM from silicon p-n junction specimens that were etched in ammonium fluoride solution. Experimental SE micro-spectroscopy and numerical simulations indicate that Fermi level pinning occurred on the surface of the treated-specimen, and that the doping contrast can be explained in terms of the ionisation energy integral for SEs, which is a function of the dopant concentration, and surface band-bending effects that prevail in the mechanism for doping contrast as patch fields from the specimen are suppressed.

(Invited) Physics of Electronic Transport in Low-Dimensionality Materials for Future FETs

The scaling of electronic devices has continued unabated for the past 5 decades, despite repeated predictions of the "end of scaling". The "more than Moore" slogan has been, and still is, viewed by industry as a need to explore realistic low-to-medium-risk avenues, some already in production -- such as strained Si/Ge or high-κ dielectrics, some yet to be translated to products in the near future or never -- such III-V semiconductors or tunnel-FETs. On the contrary, Academia has looked far ahead, even beyond carbon-based electronics (carbon nanotubes, graphene, nanoribbons). Now that the ULSI technology is looking at a feature size of 5 nm by 2026, even more “improbable” alternatives are considered, including transition metal dichalcogenides (TMDs), silicene/ane, germanene/ane (together with other *enes and *anes), topological insulators, Weyl semimetals, and other strongly correlated fermion systems. Here I will first discuss the fact that, if we really wish to scale to 5 nm, simple electrostatic scaling laws demand that we take two-dimensional materials very seriously, despite their thermodynamic instability (Mermin-Wagner theorem) and the related technological difficulties. I will first consider how electronic transport in non mirror-symmetric 2D crystals (e.g., silicene, germanene, stanene, TMDs of the 1T/T’ crystal structure) may be severely affected by coupling of the electrons with the acoustic flexural modes (ZA-phonons). I will then consider whether graphene has any chance of replacing Si by looking at how the extremely promising electronic properties it exhibits in its ideal form become much less interesting when it becomes a component of some non-ideal structure (such when supported and gated and/or in nanoribbon form). Finally, I will discuss a couple of very interesting admittedly improbable but fun ideas: 1. The Bose-Einstein condensation in bilayer systems (motivating UT-Austin’s BiSFETs) as an example of how issues of practical implementation may regrettably transform an excellent idea into a pure academic exercise; and 2. Monolayer tin (“stannanane”) as a 2D topological insulator with potential applications in spintronics and low-power high-performance devices (… assuming we can make it, of course…). For the entire discussion I will keep density functional theory (DFT), empirical pseudopotentials, and transport equations in the background. This work qas done in collaboration with Shela Aboud, Bo Fu, Jiseok Kim, Sudarshan Narayanan, Ana Suarez Negreira, Zhun-Yong Ong, Cathy Sachs, and William Vandenberghe.

(Invited) The Multidisciplinary Approach: A Common Trend for ULSI and Thin Film Technology

The scaling down of microelectronics devices has been following the Moore’s law since many years. The capability of integration till increasing, the new integration more and more combines the devices and circuits to other than electrical functions, physical, chemical, or biological functions. These new objects need a multidisciplinary approach to insert the new devices in systems, in terms of applications. The fields of application can be very wide and should answer to the societal needs. The corresponding objects are preferentially communicating and smart in many cases. The design of these objects must combine the traditional electronics with digital circuits, the interface with the humans thanks to displays, but also many other functions of detections, communications, transmissions, signal treatments and actuations. This paper tries to show the diversity of the technologies, from ULSI to TFTs, able to answer to this new trend and gives some directions in order to well form the future engineers and researchers.

Review and Projections of Integrated Cooling Systems for Three-Dimensional Integrated Circuits

In an effort to increase processor speeds, 3D IC architecture is being aggressively pursued by researchers and chip manufacturers. This architecture allows extremely high level of integration with enhanced electrical performance and expanded functionality, and facilitates realization of VLSI and ULSI technologies. However, utilizing the third dimension to provide additional device layers poses thermal challenges due to the increased heat dissipation and complex electrical interconnects among different layers. The conflicting needs of the cooling system requiring larger flow passage dimensions to limit the pressure drop, and the IC architecture necessitating short interconnect distances to reduce signal latency warrant paradigm shifts in both of their design approach. Additional considerations include the effects due to temperature nonuniformity, localized hot spots, complex fluidic connections, and mechanical design. This paper reviews the advances in 3D IC cooling in the last decade and provides a vision for codesigning 3D IC architecture and integrated cooling systems. For heat fluxes of 50–100 W/cm2 on each side of a chip in a 3D IC package, the current single-phase cooling technology is projected to provide adequate cooling, albeit with high pressure drops. For future applications with coolant surface heat fluxes from 100 to 500 W/cm2, significant changes need to be made in both electrical and cooling technologies through a new level of codesign. Effectively mitigating the high temperatures surrounding local hot spots remains a challenging issue. The codesign approach with circuit, software and thermal designers working together is seen as essential. The through silicon vias (TSVs) in the current designs place a stringent limit on the channel height in the cooling layer. It is projected that integration of wireless network on chip architecture could alleviate these height restrictions since the data bandwidth is independent of the communication lengths. Microchannels that are 200 μm or larger in depth are expected to allow dissipation of large heat fluxes with significantly lower pressure drops.

Novel RF PVD Ti Technology for HAR Structure Applications

Titanium (Ti) liners have been widely used in ULSI technology to improve contact/via resistance. As devices scale down to 32nm and below, Ti extends its application as a wetting layer for planar metal gate and 3D tri-gate structures. To meet the accompanying challenges, a novel RF/DC PVD chamber was developed, operating with capacitively coupled plasma (CCP) and a DC source to create high metal-ion flux with low energy. The new technology reduces overhang and increases bottom coverage. This paper presents the chamber’s tuning knobs that fulfill different process requirements for contact and metal-gate, thereby widening the process window for effective gap fill.

Atomic Layer Deposition of TiO2 on Surface Modified Nanoporous Low-k Films

This paper explores the effects of different plasma treatments on low dielectric constant (low-k) materials and the consequences for the growth behavior of atomic layer deposition (ALD) on these modified substrates. An O2 and a He/H2 plasma treatment were performed on SiCOH low-k films to modify their chemical surface groups. Transmission FTIR and water contact angle (WCA) analysis showed that the O2 plasma changed the hydrophobic surface completely into a hydrophilic surface, while the He/H2 plasma changed it only partially. In a next step, in situ X-ray fluorescence (XRF), ellipsometric porosimetry (EP), and Rutherford backscattering spectroscopy (RBS) were used to characterize ALD growth of TiO2 on these substrates. The initial growth of TiO2 was found to be inhibited in the original low-k film containing only Si-CH3 surface groups, while immediate growth was observed in the hydrophilic O2 plasma treated film. The latter film was uniformly filled with TiO2 after 8 ALD cycles, while pore filling was delayed to 17 ALD cycles in the hydrophobic film. For the He/H2 plasma treated film, containing both Si-OH and Si-CH3 groups, the in situ XRF data showed that TiO2 could no longer be deposited in the He/H2 plasma treated film after 8 ALD cycles, while EP measurements revealed a remaining porosity. This can be explained by the faster deposition of TiO2 in the hydrophilic top part of the film than in the hydrophobic bulk which leaves the bulk porous, as confirmed by RBS depth profiling. The outcome of this research is not only of interest for the development of advanced interconnects in ULSI technology, but also demonstrates that ALD combined with RBS analysis is a handy approach to analyze the modifications induced by a plasma treatment on a nanoporous thin film.

Plasma processing of low-k dielectrics

This paper presents an in-depth overview of the present status and novel developments in the field of plasma processing of low dielectric constant (low-k) materials developed for advanced interconnects in ULSI technology. The paper summarizes the major achievements accomplished during the last 10 years. It includes analysis of advanced experimental techniques that have been used, which are most appropriate for low-k patterning and resist strip, selection of chemistries, patterning strategies, masking materials, analytical techniques, and challenges appearing during the integration. Detailed discussions are devoted to the etch mechanisms of low-k materials and their degradation during the plasma processing. The problem of k-value degradation (plasma damage) is a key issue for the integration, and it is becoming more difficult and challenging as the dielectric constant of low-k materials scales down. Results obtained with new experimental methods, like the small gap technique and multi-beams systems with separated sources of ions, vacuum ultraviolet light, and radicals, are discussed in detail. The methods allowing reduction of plasma damage and restoration of dielectric properties of damaged low-k materials are also discussed.

X-Ray Induced Depth Profiling of Ion Implantations into Various Semiconductor Materials

The continuing shrinking of the component dimensions in ULSI technology requires junction depths in the 20-nm regime and below to avoid leakage currents. These ultra shallow dopant distributions can be formed by ultra-low energy (ULE) ion implantation. However, accurate measurement techniques for ultra-shallow dopant profiles are required in order to characterize ULE implantation and the necessary rapid thermal annealing (RTA) processes.

<i>In Situ</i> Studies of III-V Surfaces and High-K Atomic Layer Deposition

Atomic layer deposition (ALD) of high dielectric constant (high-k) materials for ULSI technologies is now widely adopted in Si-based CMOS production. Extending the scaling of integrated circuit technology has now resulted in the investigation of transistors incorporating alternative channel materials, such as III-V compounds. The control of the interfacial chemistry between a high-k dielectric and III-V materials presents a formidable challenge compared to that surmounted by Si-based technologies. The bonding configuration is obviously more complicated for a compound semiconductor, and thus an enhanced propensity to form interfacial defects is anticipated, as well as the need for surface passivation methods to mitigate such defects. In this work, we outline our recent results using in-situ methods to study the ALD high-k/III-V interface. We begin by briefly summarizing our results for III-As compounds, and then further discuss recent work on III-P and III-Sb compounds. While arsenides are under consideration for nMOS devices, antimonides are of interest for pMOS. InP is under consideration for quantum well channel MOS structures in order to serve as a better nMOS channel interface. In all cases, a high-k dielectric interface is employed to limit off-state tunneling current leakage.

(Invited) Vertical Channel Thin Film Transistor: Improvement Approach Similar to Multigate Monolithic CMOS Technology

The silicon based thin film transistors (TFTs) technology evolution is governed by electrical performances that are needed for many applications. Previous papers highlighted the influence of the process, the quality and the nature of the channel material on their electrical properties. TFTs had as well channel parallel to the substrate surface as quasi-vertical channels. This last choice allows an increase of the equivalent current density flowing in the circuit thanks to a shorter channel length and a higher channel width, for the same lithographical node. However, the drain-source leakage current was measured proportional to the source-drain face-to-face area, while Ion is proportional to channel width. This behavior was also observed in vertical monolithic structures. To minimize this effect two main ways are proposed: decreasing the scale, or including a physical barrier between source and drain. We will see that these approaches are really similar to ULSI technology ones.

Efficient Silicon Light-Emitting-Diodes with a p-Si/Ultrathin SiO2/n-Si Structure

We report the efficient enhancement of light emission from silicon crystal by covering the silicon surface with an ultrathin (several nm) SiO2layer. The photoluminescence of Si band edge emission (1.14 μm band) at room temperature is enhanced by two orders of magnitude. Compared with a p-Si/n-Si diode, light emission from a p-Si/SiO2/n-Si diode by current injection via direct tunneling is enhanced by more than 3 orders of magnitude. The light-emission enhancement is attributed to the diminishment of nonradiation recombination at the surface/interface and to the space confinement of the carrier recombination. The simple structure and low operating bias (approximately 1 volt) of our light emitting diodes supply a new choice for realizing efficient current injection light source in silicon compatible with conventional ULSI technology.

Nitrided Tetragonal $\hbox{ZrO}_{2}$ as the Charge-Trapping Layer for Nonvolatile Memory Application

Employment of a tetragonal ZrO2 film as the charge-trapping layer for nonvolatile memory was investigated and the NH3 nitridation effect of the ZrO2 film on memory performance was also explored in this letter. The permittivity of the tetragonal ZrO2 film is slightly reduced from 38.7 to 36.9 after nitridation; nevertheless, nitridation introduces more trapping sites and passivates the grain boundary channel which results in a high operation speed in terms of 2.6-V flatband voltage shift by programming at +10 V for 10 ms and a good retention characteristic with 20.2% charge loss after ten-year operation at 125degC, both are superior to that without NH3 nitridation. Most importantly, the process is fully compatible with existent ULSI technology and paves the way to adopt a high-permittivity crystalline dielectric as the charge-trapping layer for future high-performance nonvolatile memory.