Types Of MOSFETs Research Articles

Basic Failure Modes of CMOS Devices and the Improvements

Mosfets are the most important and basic part of integrated circuits, which the modern information network relies on. Combing a great number of mosfets, most integrated circuits would require the constituent part of themselves work in a stable and reliable state. Though, having been improved both in materials and constructures for tens of years, various types of mosfets still face the great danger of failure. This article would generally introduce this important issue of integrated circuit both on the issue and the methods of improvements, based on former researches, first making the classifications according to the formation mechanism of the failure modes, with an example of each failure mode, then introducing the train of thought of each kind of failure modes showed above. This article would be a summary on most common failure modes of cmos devices, with the formation mechanisms and their solutions, though not being comprehensive about most situations, it is supposed to be a reference on cmos circuit design, which may help to choose the specific devices and to improve the performance of the circuit in actual productions.

Investigation of Threshold Voltage Instability and Bipolar Degradation in 3.3 kV Conventional Body Diode and Embedded SBD SiC MOSFET

The 3.3 kV SiC MOSFETs are essential for traction applications, so it is important to investigate the reliability of the recently developed high voltage MOSFETs and power modules as they are believed to be more susceptible to the effects of basal plane dislocations (BPDs). This paper presents measurement results and analysis of bipolar degradation and threshold voltage instability in 3.3 kV SiC MOSFETs having two distinct kinds of integrated diode, conventional body diode and embedded Schottky Barrier Diode (SBD). No bipolar degradation was observed both in MOSFET with conventional body diode and with embedded SBD after accumulated test with 100 hours each of 200%, 400% and 600% rated current stress in the 3rd quadrant of operation. However, the output characteristics show 1% (~0.2 mΩ) and 2% (~0.4 mΩ) increase in on resistance (RDS(on)) and 11% (0.23 V) and 5% (0.1 V) increase in threshold voltage (VTH), respectively, after total bipolar degradation test in the case of the MOSFET with conventional body diode and up to 74 hrs of 600% rated current stress in the case of the MOSFET with embedded SBD at 70°C. A rapid large negative VTH shift was observed in the MOSFETs with embedded SBD after ~ 74 hrs of 600% rated current stress. After accumulated Bias Temperature Instability (BTI) test at 150°C, the VTH value at 25°C has increased by 9.7% (0.14 V) and 14.5% (0.2 V) for the MOSFET with conventional body diode and with embedded SBD, respectively, while RDS(on) increased by 1mΩ at 25°C and by 5mΩ at 150°C, for both types of MOSFETs.

Review of: "The switching speed of this type is limited, for example, 1 KHz to 50 KHz, which is generally between two types of BJT and MOSFET"

Review of: "The switching speed of this type is limited, for example, 1 KHz to 50 KHz, which is generally between two types of BJT and MOSFET"

Review of: "The switching speed of this type is limited, for example, 1 KHz to 50 KHz, which is generally between two types of BJT and MOSFET. Because of its very high input impedance, it is very sensitive and is mostly used in induction furnaces to amplify the voltage range"

Review of: "The switching speed of this type is limited, for example, 1 KHz to 50 KHz, which is generally between two types of BJT and MOSFET. Because of its very high input impedance, it is very sensitive and is mostly used in induction furnaces to amplify the voltage range"

Ge-on-insulator fabrication based on Ge-on-nothing technology

Ge-on-Insulator (GOI) is considered to be a necessary structure for novel Ge-based devices. This paper proposes an alternative approach for fabricating GOI based on the Ge-on-Nothing (GeON) template. In this approach, a regular macropore array is formed by lithography and dry etching. These pores close and merge upon annealing, forming a suspended monocrystalline Ge membrane on one buried void. GOI is fabricated by direct bonding of GeON on Si carrier substrates, using an oxide bonding interface, and subsequent detachment. The fabricated GOI shows uniform physical properties as demonstrated using micro-photoluminescence measurements. Its electrical characteristics and cross-sectional structure are superior to those of Smart-CutTM GOI. To demonstrate its application potential, back-gate GOI capacitors and MOSFETs are fabricated. Their characteristics nicely agree with the theoretically calculated one and show typical MOSFET operations, respectively, which indicates promising Ge crystallinity. This method, therefore, shows the potential to provide high-quality GOI for advanced Ge application devices.

Review of: "The switching speed of this type is limited, for example, 1 KHz to 50 KHz, which is generally between two types of BJT and MOSFET"

Review of: "The switching speed of this type is limited, for example, 1 KHz to 50 KHz, which is generally between two types of BJT and MOSFET"

A New Type of Si-Based MOSFET for Radiation Reinforcement.

This paper thoroughly analyses the role of drift in the sensitive region in the single-event effect (SEE), with the aim of enhancing the single-particle radiation resistance of N-type metal-oxide semiconductor field-effect transistors (MOSFETs). It proposes a design for a Si-based device structure that extends the lightly doped source-drain region of the N-channel metal-oxide semiconductor (NMOS), thereby moderating the electric field of the sensitive region. This design leads to a 15.69% decrease in the charge collected at the leaky end of the device under the standard irradiation conditions. On this basis, a device structure is further proposed to form a composite metal-oxide semiconductor (MOS) by connecting a pn junction at the lightly doped source-drain end. By adding two charge paths, the leakage collection charge is further reduced by 13.85% under standard irradiation conditions. Moreover, the deterioration of the drive current in the purely growing lightly doped source-drain region can be further improved. Simulations of single-event effects under different irradiation conditions show that the device has good resistance to single-event irradiation, and the composite MOS structure smoothly converges to a 14.65% reduction in drain collection charge between 0.2 pC/μm and 1 pC/μm Linear Energy Transfer (LET) values. The incidence position at the source-to-channel interface collects the highest charge reduction rate of 28.23%. The collecting charge reduction rate is maximum, at 17.12%, when the incidence is at a 45-degree angle towards the source.

Review of: "The switching speed of this type is limited, for example, 1 KHz to 50 KHz, which is generally between two types of BJT and MOSFET"

Review of: "The switching speed of this type is limited, for example, 1 KHz to 50 KHz, which is generally between two types of BJT and MOSFET"

Speed-Power Efficient Novel CMOS Unary-to-Ternary Encoder

A new full-custom design of Unary-to-Ternary-Encoder (UTE) using standard Enhancement-Type-Metal–Oxide-Semiconductor-Field-Effect-Transistor reporting low-PDP (Power-Delay-Product) and low-area is presented. The inherent pass characteristic of the E-MOS-transistor is exploited here to develop the proposed Ternary-Encoder. Theoretical aspects along with the operation of proposed 9:2 and 27:3 UTE are discussed. The complete UTE is designed and optimized on 32 nm standard CMOS technology at 0.9 V supply-rail and 27°C. Ternary digits “0”, “1” and “2” are represented with 0 V, 0.45 V and 0.9 V respectively. The proposed design is validated through extensive T-Spice front-end transient simulations with all possible test patterns. The layout of the proposed design is completed on 32 nm Single-Poly-Double-Metal (SPDM) CMOS--Technology. After DRC and LVS post-layout simulation with extracted parasitic and 1 fF load, is carried out. The valuated performance of the 9:2 UTE is next compared with a recent candidate design to this end, from open literature to benchmark. The Power-Delay-Product (PDP) of proposed UTE is measured by applying ±10% supply variation from nominal on slow, typical and fast MOSFET at −40°C, 27°C and 85°C. Finally, the speed-power characteristic of the proposed 9:2 UTE is explored under different load conditions from 1 to 10 fF.

The Influence of Special Environments on SiC MOSFETs.

In this work, the influences of special environments (hydrogen gas and high temperature, high humidity environments) on the performance of three types of SiC MOSFETs are investigated. The results reveal several noteworthy observations. Firstly, after 500 h in a hydrogen gas environment, all the SiC MOSFETs exhibited a negative drift in threshold voltage, accompanied by an increase in maximum transconductance and drain current (@ VGS/VDS = 13 V/3 V). This phenomenon can be attributed to that the hydrogen atoms can increase the positive fixed charges in the oxide and increase the electron mobility in the channel. In addition, high temperature did not intensify the impact of hydrogen on the devices and electron mobility. Instead, prolonged exposure to high temperatures may induce stress on the SiO2/SiC interface, leading to a decrease in electron mobility, subsequently reducing the transconductance and drain current (@ VGS/VDS = 13 V/3 V). The high temperature, high humidity environment can cause a certain negative drift in the devices' threshold voltage. With the increasing duration of the experiment, the maximum transconductance and drain current (@ VGS/VDS = 18V (20 V)/3 V) gradually decreased. This may be because the presence of moisture can lead to corrosion of the devices' metal contacts and interconnects, which can increase the devices' resistance and lead to a decrease in the devices' maximum transconductance and drain current.

Measurement and Analysis of Body Diode Stress of 3.3 kV Sic-Mosfets with Intrinsic Body Diode and Embedded SBD

SiC MOSFETs display reliability issues related to the quality of SiO2/SiC interface and bulk material due to the presence of near interface traps and point and extended material defects [1]. These material related issues give rise to a degradation of device reliability and ruggedness. One of them are basal plane dislocations (BPDs) introduced in the drift-layer during the epitaxial growth process which causes a s.c. bipolar degradation. Growth and movement of BPDs fueled by recombination energy has a very significant impact on conduction loss and on-resistance degradation. For 3.3 kV voltage capability, the probability of the appearance of BPDs is greater because the drift region is about three times larger compared to 1.2 kV devices [2-3]. We present measurement results and analysis of bipolar degradation in 3.3 kV MOSFETs with conventional body diode and embedded schottky barrier diode (SBD). The measurements were performed applying 50 % and 80 % of rated current with duty cycle 80 %, under total time of 100 hrs at constant case temperature of 54 °C. The 3rd-quadrant performance of both types of MOSFETs in pre-stress conditions was characterized at 25 and 150 °C with different gate biases of -10 V, 0 V, and +17 V. To evaluate the bipolar degradation, the diode conduction characteristics were measured at 25 °C after different stressing times by diode conduction the MOSFET output characteristics were measured at 25 and 54 °C before and after stressing the intrinsic body diode and embedded SBD. No VSD shift was observed in diode conduction characteristics. The results indicate that the MOSFETs were fabricated on appropriate material with a sufficiently low number basal plane dislocation (BPD). The on-state resistance with VGS = +17 V was decreased by temperature due to increased JFET resistance rather than bipolar degradation. On the other hand, the on-state resistance with VGS = +11 V was impacted by the increased temperature and VTH instability.

Experimental analysis of phase shift modulation methods effects on EMI in dual active bridge DC-DC converter

Dual active bridge DC-DC converters (DAB) are one of the bidirectional converters and mainly used in electric vehicles and micro grids. With the increasing number of electric vehicles in use, and the increasing amount of batteries in these vehicles and rapidly spanning micro grids, the importance of DAB converters has increased and they are expected to be smaller in size and operate at higher power levels. The reduction in size has increased the importance of power density and efficiency, which are two significant parameters of DAB circuits. One of the methods to increase efficiency and power density is to increase the switching frequency. However, with the increase at the switching frequency, electromagnetic interference (EMI) in the DAB circuit also increases.In this manuscript, the change in the EMI values emitted by conduction, according to the phase shift modulation methods at DAB converters are evaluated. Also the effect of type of MOSFETs on conducted EMI is examined. Prototypes of the DAB converters by using Si and SiC MOSFETs with power rating of 1 kW are designed and developed. Switching frequency of converter is 25 kHz and leakage inductance is determined 81uH and 75uH. Si based circuit is operated with %88.5 efficiency. SiC based circuit is also operated with %88 efficiency. The designed circuits are operated using the phase shift modulations SPS and DPS. Conducted emission noise emitted by these circuits are analyzed by dividing them into common mode and difference mode noises. It has been observed that the EMI value when using SPS method is 15–20 dBµV lower than the EMI when using DPS method. The relationship between the measured noises and the efficiency of the circuits was observed.

Effects of 5 MeV proton irradiation on 4H-SiC lateral pMOSFETs on-state characteristics

Silicon carbide (SiC) MOSFETs are often used in harsh environments where they are exposed to ionizing radiation. This paper investigates the effects of high-energy proton irradiation on SiC MOSFETs, with a particular emphasis on the on-state characteristics of lateral pMOSFETs. By comparing with the lateral 4H-SiC nMOSFET after irradiation in our prior work, we observed the deviations of important electrical parameters. As the irradiation dose increases, the threshold voltage (VTH) of pMOSFETs is negatively shifted and has more negative offsets than that of nMOSFETs. This is due to two factors which affect VTH after irradiation: the near interface oxide traps (NIOTs) and the interface traps (Nit). These two factors compensate each other for nMOSFETs, but strengthen each other for pMOSFETs. It is found that an increase in the density of interface traps (Dit) in both types of MOSFETs after irradiation. However, unlike the nMOSFET, the pMOSFET has a decreasing field effect mobility (μFE) with the increase of irradiation dose. We believed that besides the effect of Dit on μFE, NIOTs have a more profound influence on μFE, resulting in different changes between nMOSFETs and pMOSFETs’ μFE.

Evaluation of 4H‐SiC MOSFET transfer characteristics using machine‐learning techniques

The performance of 4H silicon carbide (SiC) MOSFETs critically depends on the quality of the SiC/silicon oxide interface, which typically contains a high density of interface traps. To solve this problem, fast and reliable characterization methods are required. The commonly used evaluation schemes for 3-terminal transfer characteristics, however, neglect the presence of interface traps. Here, a method based on machine-learning techniques is presented which extracts reliable performance parameters from transfer characteristics of 4H-SiC MOSFETs including a quantitative estimate of the density of interface traps. This method is successfully validated by comparison with Hall-effect measurements and applied to various MOSFET types.

Electrochemical modeling in a building blocks’ way

Good modeling of electrochemical systems should serve as not only a practical instrument, but also an insight straight into the essence at a glance, in pursuit of which, parted modeling paths following the first-principles theories and the external-characteristics fitting tend to communicate, with the actual possibility in making the two more consistent. We report a new modeling framework and method that fulfills modeling aimed at multi-physical consistency in the electrochemical and analogous areas. With such novel ideas, one scalable full-cell model for lithium-ion battery (LIB) is established using the time-variant transmission line (TVTLM) micro-units just like building blocks. The model provides the convenience to dive into the first-principles mechanisms, along with the superiority in approximating the external characteristics, hence bridging the two paths. To highlight the intuitiveness and the universality, the modeling framework and method is migrated to facilitate the modeling of other types of lithium batteries, N-channel MOSFET and selective bio-membrane. Our ideas suggest a commonly applicable guidance to the modeling of a wide range of electrochemical devices.

IDENTIFICATION OF WHITE NOISE AND 1/f IN CURRENT MIRROR CONFIGURATION BASED ON VDS MOSFET

Identifying noise in the Current Mirror (CM) circuit is essential to locate noise signals in biosensor applications so that measurements become more accurate and precise. There are two dominant types of noise: white noise, which consists of thermal noise and shot noise, and also low-frequency noise (1/f noise). The main component of the CM circuit is the BS250 type MOSFET, which works by varying the width of the charge carrier channelcontrolled by the voltage at the gate. When the drain is given a voltage, electrons will flow from the source to the drain which generates the noise.This study was carried out to identify the noise in the CM configuration by varying the reference voltage of MOSFET using the PCI-6221 card data integrated with the LabVIEW program. The reference voltage values ​​used are 1 mV, 10 mV, and 100 mV to determine the effect of the input voltage on the CM circuit noise signal, while the measurement frequency is varied from 0.1 Hz to 100 kHz with a resolution of 0.1 Hz. The results show that the noise characteristics vary with the applied voltage, which will increase at a higher voltage. Analysis of 1/f noise at frequencies up to 0.2 Hz has a gradient increase of up to 10 times for each given voltage value. Based on the value of the data distribution on the white noise measurement, it shows that a voltage of 100 mV produces the highest noise with an average of 3.62 × 10-7 Vrms/Hz1/2. The results of this study are used in the design of CM circuits with minimal noise.

Gate-switching-stress test: Electrical parameter stability of SiC MOSFETs in switching operation

We present a new, simplified, pulsed-gate stress test approach to determine the electrical parameter stability of SiC MOSFETs under application-like conditions over a lifetime. By comparing the results to an application test under the same conditions, we demonstrate that our test procedure reflects most realistically worst-case, end-of-life parameter drifts that occur in typical SiC MOSFET switching applications.

Synergistic Effect of Electrical Stress and Neutron Irradiation on Silicon Carbide Power MOSFETs

The synergistic effect of radiation and bias voltage for the commercial silicon carbide (SiC) power MOSFETs was investigated by 14-MeV neutron irradiation in this article. The types of C3M0065090D and C2M0080120D commercial SiC power MOSFETs from CREE studied in this article show consistent changes after the 14-MeV neutron irradiation. The results show that the devices biased during irradiation experienced more degradation than that only irradiated and biased devices. Compared with the devices only irradiated and biased, the devices biased during irradiation experienced an additional decrease in saturation current and a further decrease in peak transconductance. The defects in the devices were characterized by the low-frequency noise (LFN) and deep-level transient spectrum (DLTS) methods. The results show that the synergistic effect increased the defect concentration of the device, resulting in further degradation of the electrical performance of the device compared to the control group without a bias voltage. The defect characterization shows that the drain–source voltage leads to the accumulation of carbon and silicon vacancies induced by irradiation at the interface, which results in intensified radiation damage and significant changes in the performance of the device at low neutron fluence.

The Influence of Repetitive UIS on Electrical Properties of Advanced Automotive Power Transistors

This paper investigates a degradation of three types of automotive power MOSFETs through repetitive Unclamped Inductive Switching (UIS) test typically used to evaluate the avalanche robustness of power devices. It is not uncommon in switching applications that greater than the planned voltage for voltage spikes can occur, so even the best electronic designs may encounter frequent avalanche events. Hence, there is a need to analyse the impact of repetitive avalanching on the electrical performance of power transistors. This article focused on the shift of main electrical parameters: on-resistance R_{ON}, breakdown voltage V_{BR}, threshold voltage V_{TH}, and corresponding characteristics, as well as capacitances. Analysis proved that DMOS transistors are less vulnerable to repetitive avalanching. The most impacted parameter was on-resistance R_{DSon}, where a 14 % increase was observed after 6 x 10^7 stress pulses. The parameters shift is attributed to hot carrier injection in the space charge region of blocking PN junction and involves mainly defects generation/activation in the drain side region of the gate oxide. For the TrenchMOS transistor, a significant shift of I-V curves was observed with considerable impact on the R_{ON} where an increase of 22 % was observed. The trench corner is verified to be the mainly degraded region by Synopsys Technology Computer Aided Design (TCAD) simulations. Degradation of drain-gate capacitance C_{DG} and input capacitance C_{in} was observed in all three types of analysed structures. DLTS was used to verify the generation/activation of defects invoked by stress. An increase of DLTS signal corresponding to energy levels of oxygen vacancies and impurities in SiO_2 and on interfaces were detected on stressed samples.

Simulation of low frequency noise in buried-channel MOSFET by a Green’s function-based numerical trap level model

The depletion mode Buried Chanel (BC) MOSFETs are known for their reduced Low Frequency Noise (LFN) as compared with normal Surface Channel (SC) MOSFETs in the application of Charge-Coupled Devices (CCDs) and CMOS imagers. To investigate the BC MOSFETs’ LFN mechanism comprehensively, we have developed a physical-based numerical device level simulator that accounts for the LFN contribution from each single individual oxide trap. During the simulation, the trapping current amplitude ΔID matrices are extracted efficiently by the potential-current based Green’s function. The trap capture and emission time constants are calculated via Shockley–Read–Hall (SRH) theory with Wentzel-Kramers-Brillouin (WKB) tunneling approximation. To valid our simulator, both BC and SC type MOSFETs are designed and fabricated in a CMOS imager compatible process for noise measurement and comparison. Quantitatively agreement has been obtained for both types of MOSFETs in terms of LFN spectra on a wide biasing range from the extracted process-based oxide traps’ geometry and energy sites. It reveals that the low noise operation of BC MOSFETs is inseparable from both the ΔID suppression effect and the traps’ activation energy.