Speed-Power Efficient Novel CMOS Unary-to-Ternary Encoder

Abstract

A new full-custom design of Unary-to-Ternary-Encoder (UTE) using standard Enhancement-Type-Metal–Oxide-Semiconductor-Field-Effect-Transistor reporting low-PDP (Power-Delay-Product) and low-area is presented. The inherent pass characteristic of the E-MOS-transistor is exploited here to develop the proposed Ternary-Encoder. Theoretical aspects along with the operation of proposed 9:2 and 27:3 UTE are discussed. The complete UTE is designed and optimized on 32 nm standard CMOS technology at 0.9 V supply-rail and 27°C. Ternary digits “0”, “1” and “2” are represented with 0 V, 0.45 V and 0.9 V respectively. The proposed design is validated through extensive T-Spice front-end transient simulations with all possible test patterns. The layout of the proposed design is completed on 32 nm Single-Poly-Double-Metal (SPDM) CMOS--Technology. After DRC and LVS post-layout simulation with extracted parasitic and 1 fF load, is carried out. The valuated performance of the 9:2 UTE is next compared with a recent candidate design to this end, from open literature to benchmark. The Power-Delay-Product (PDP) of proposed UTE is measured by applying ±10% supply variation from nominal on slow, typical and fast MOSFET at −40°C, 27°C and 85°C. Finally, the speed-power characteristic of the proposed 9:2 UTE is explored under different load conditions from 1 to 10 fF.