Two-stage Low Noise Amplifier Research Articles

A correlation noise spectrometer for flicker noise measurement in graphene samples

We present a high-resolution digital correlation spectrum analyzer for the measurement of low frequency resistance fluctuations in graphene samples. The system exploits the cross-correlation method to reject the amplifiers’ noise. The graphene sample is excited with a low-noise DC current. The output voltage is fed to two two-stage low-noise amplifiers connected in parallel; the DC signal component is filtered by a high-pass filter with a cutoff frequency of 34 mHz. The amplified signals are digitized by a two-channel synchronous ADC board; the cross-periodogram, which rejects uncorrelated amplifiers’ noise components, is computed in real time. As a practical example, we measured the noise cross-spectrum of graphene samples in the frequency range from 0.153 Hz to 10 kHz, both in two- and four-wire configurations, and for different bias currents. We report here the measurement setup, the data analysis and the error sources.

Challenges in On-Chip Antenna Design and Integration With RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems

This paper investigates design considerations and challenges of integrating on-chip antennas in nanoscale CMOS technology at millimeter-wave (mm-wave) to achieve a compact front-end receiver for 5G communication systems. Solutions to overcome these challenges are offered and realized in digital 28-nm CMOS. A monolithic on-chip antenna is designed and optimized in the presence of rigorous metal density rules and other back-end-of-the-line (BEoL) challenges of the nanoscale technology. The proposed antenna structure further exploits ground metallization on a PCB board acting as a reflector to increase its radiation efficiency and power gain by 37.3% and 9.8 dB, respectively, while decreasing the silicon area up to 30% compared to the previous works. The antenna is directly matched to a two-stage low noise amplifier (LNA) in a synergetic way as to give rise to an active integrated antenna (AIA) in order to avoid additional matching or interconnect losses. The LNA is followed by a double-balanced folded Gilbert cell mixer, which produces a lower intermediate frequency (IF) such that no probing is required for measurements. The measured total gain of the AIA is 14 dBi. Its total core area is 0.83 mm 2 while the total chip area, including the pad frame, is 1.55 × 0.85 mm 2 .

GaAs MMIC Low Noise Amplifier With Integrated High-Power Absorptive Receive Protection Switch

This letter reports a GaAs monolithic microwave integrated circuit (MMIC) low noise amplifier (LNA) with integrated high-power absorptive receive protection switch realized using 0.13- $\mu \text{m}$ GaAs pHEMT process. On-the-chip current distributed, resonant shunt FET switch configuration is employed for higher power handling. FET stacking technique is used to reduce the effective noise figure (NF). A two-stage LNA with integrated high power switch, forming each arm in a balanced configuration is employed to realize a monolithic LNA with integrated absorptive receive protection switch. This novel MMIC provides protection up to 20-W continuous wave and 2.9-dB NF, a gain of 20 dB over 9.3–9.9 GHz.

A High Gain and Forward Body Biastwo-stage Ultra-wideband Low Noise Amplifier with Inductive Feedback in 180 nm CMOS Process

This paper presents a two-stage low-noise ultra-wideband amplifier to obtain the high and smooth gain in 180nm CMOS Technology. The proposed structure has two common source stages with inductive feedback. The first stage is designed for 3GHz frequency and the second stage is designed about 8GHz. In the simulation, symmetric inductors of TSMC 0.18um CMOS technology in ADS software is used. Simulation results show high and relatively smooth S21 equal to 18.674±1.38dB, the noise figure of less than 3.7dB, the power consumption of 14.6mW with 1.2V supply voltage and suitable matching at the input (S11<-10.8dB) in 3.1 to 10.6 GHz frequency range. Moreover, IIP3 of this circuit is -9.5dBm at the 7GHz frequency.

Analysis and Design of Broadband &lt;italic&gt;LC&lt;/italic&gt;-Ladder FET LNAs Using Noise Match Network

A noise match network for the LC -ladder input network of a broadband inductively source-degenerated common-source (CS) field effect transistor (FET) low-noise amplifier (LNA) is established through noise transformation matrix to derive the noise parameters of a broadband LNA. Analytical formulas for the noise factors of a CS FET LNA with a three-section LC-ladder input network are thus obtained based on the design algorithm of optimal noise and input match developed in this paper. Two 3.7–10.5 GHz two-stage LNAs of the same topology are demonstrated using 0.15- $\mu \text{m}$ pHEMT technology to validate the design methodology. One LNA has all the fully integrated inductors and the other uses two on-chip inductors replaced by two high-Q bondwire inductors for better noise performance. The measurement results show 11-dB power gain with 2.1-dB noise figure for the LNA with the fully integrated inductors and 11-dB power gain with 1.6-dB noise figure for the LNA with two bondwire inductors, respectively.

Design of ultra‐low noise, wideband low‐noise amplifier for highly survival radar receiver

High electron mobility transistors (HEMTs) play a crucial role in microwave low-noise amplifier (LNA) and are used in radar receiver, software defined radio and digital radio frequency. A novel technique is used to design and fabricate a high-performance wideband LNA for 5.4–5.9 GHz based on fully stabilised InGaAs pseudo-morphic HEMT (pHEMT) 0.15 µm technology. With the Agilent Advanced Design System simulation tool, a C-band (5.4–5.9 GHz) two-stage LNA using pHEMT based on monolithic microwave integrated circuit (MMIC) technology has been designed: noise figure <1 dB, power gain of 18 dB, output 1 dB compression >13 dBm and OIP3 >24 dBm, lower value of input/output return loss reflects the accuracy of impedance matching network at input and output sides of amplifier, full band unconditional stability. In this study, it is shown that the InGaAs pHEMT has the ability to handle high power to make it the perfect technology candidate for highly survival radar receiver component and survival up to 37 dBm input power level is demonstrated. The circuit based in the proposed technology shows comparable low noise figure, decent gain, with high dynamic range and high survivability. Finally, the simulation results and fabricated device results are in good agreement and superior than the earlier reported design.

9.5 mW fully integrated K ‐band on–off keying receiver with −47.6 dBm sensitivity and 600 Mbit/s data rate in 90 nm CMOS

A K-band on–off keying (OOK) receiver implemented in tsmcTM 90 nm CMOS process is proposed. The proposed OOK receiver consists of a two-stage wideband low-noise amplifier, a single-to-differential envelop detector with RC lowpass filter and a 62.6 dB three-stage variable gain amplifier and DC offset compensation circuit. The OOK receiver achieved a sensitivity of −47.6 dBm at 600 Mbit/s data rate under a pseudo-random binary sequence 29–1 pattern. The receiver consumes a low power of 9.5 mW, which minimum average power is only 15.86 nW at the input power of −47.6 dBm. The chip area including test pads is 1 × 0.81 mm2.

3-10 GHz ultra-wideband LNA with continuously variable gain for wireless communication

In this letter, a two-stage low-noise amplifier (LNA) with continuously variable gain for 3–10 GHz Ultra-wideband (UWB) application has been realized in 65 nm CMOS technology. A self-biased shunt resistive feedback with source inductive degeneration topology is used to achieve wideband input matching in the first stage; the inductive-peaking technique is introduced to make the gain smooth; and common source amplifier structure is used to realize variable gain in the second stage. The LNA exhibits a continuously variable gain ranging from −13.2 dB to 16.4 dB, a minimum NF of 3.7 dB and power consumption between 11.1 mW and 16.2 mW under a 1.2 V supply voltage. Moreover, the LNA occupies silicon area of 0.12 mm2. © 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 58:1697–1699, 2016

A 11.2 mW 48–62 GHz Low Noise Amplifier in 65 nm CMOS Technology

In this paper, a wideband low noise amplifier (LNA) for 60 GHz wireless applications is presented. A single-ended two-stage cascade topology is utilized to realize an ultra-wideband and flat gain response. The first stage adopts a current-reused topology that performs the more than 10 GHz ultra-wideband input impedance matching. The second stage is a cascade common source amplifier that is used to enhance the overall gain and reverse isolation. By proper optimization of the current-reused topology and stagger turning technique, the two-stage cascade common source LNA provides low power consumption and gain flatness over an ultra-wide frequency band with relatively low noise. The LNA is fabricated in Global Foundries 65 nm RFCMOS technology. The measurement results show a maximum $$S_{21}$$S21 gain of 11.4 dB gain with a $$-$$-3 dB bandwidth from 48 to 62 GHz. Within this frequency range, the measured $$S_{11}$$S11 and $$S_{12}$$S12 are less than $$-$$-10 dB and the measured DC power consumption is only 11.2 mW from a single 1.5 V supply.

Millimeter-Wave Low-Noise Amplifier Design in 28-nm Low-Power Digital CMOS

This paper presents the design of a 60-GHz low-noise amplifier (LNA) in a 28-nm low-power (LP) bulk CMOS process. As the technology is optimized for digital LP applications, the design of millimeter-wave (mm-wave) circuits requires high-frequency design and modeling of all active and passive devices. This includes the development of a suitable RF-transistor layout, as well as transmission lines and high- $Q$ capacitors. The mm-wave circuit design aspects are further discussed with considerations about possible dc-distribution approaches, broadband matching networks, and optimum transistor loads. The proposed approach and device models have been validated with the fabrication and characterization of a two-stage 60-GHz LNA. This circuit exhibits 13.8 dB of power gain, 18 GHz of bandwidth, 4 dB of minimum noise figure, and an input referred 1-dB compression point at $-$ 12.5 dBm consuming 24 mW of dc power. Based on this performance and to the authors’ best knowledge, the presented amplifier shows the highest reported value for a commonly used figure-of-merit of 60-GHz LNAs.

A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects

This paper explores the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design. HPC interconnects demand very high (≥ 10 Gb/s) transmission rates using ultraefficient (~ 1 pJ/bit) transceivers over extremely short (≤ 100 cm) ranges. In an attempt to design such wireless interconnects, first a model for the wireless communication channel properties is developed. The use of CMOS-based energyefficient on-off keying (OOK) transceiver architectures operating in the 60-90 GHz bands is considered as a practical solution. In order to address strict performance requirements of wireless HPC interconnects, and taking advantage of the recent developments in device scaling, compact low-power and innovative circuits based on novel double-gate MOSFETs (DG-MOSFETs) are proposed in the implementation of the architecture. The performance of a compact low-noise amplifier (LNA) design using common source (CS) inductive degeneration with 32 nm DGMOSFETs is investigated by quantitative analysis and simulation. The proposed inductor-less two-stage cascode cascade LNA is optimized for 90 GHz operation and has the advantage of gain switching over its CMOS counterpart without the use of additional switching transistors, which makes it remarkably power efficient and faster. As further examples of efficient and compact DG-MOSFET circuits for OOK transceiver design, a three-stage CS 5 dB tunable power amplifier operating up to 90 GHz, and a novel 90 GHz voltage controlled oscillator are also presented. This is followed by the proposal of an array of four monopole antennas studied using full-wave EM solver.

Ultra‐wideband wireless receiver front‐end for high‐speed indoor applications

Low-noise, ultra-wideband (UWB) wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

An X-Band Low Noise Amplifier Design for Marine Navigation Radars

In this paper, the design of a 9.1 GHz Low Noise Amplifier (LNA) of a RADAR receiver that is used in the Navy is presented. For the design of the LNA, we used GaAs Field-Effect Transistors (FETs) from Agilent ADS component library. In order to keep the cost of the circuit in low prices and the performance high, we design a two-stage LNA.

65-nm CMOS Dual-Gate Device for Ka-Band Broadband Low-Noise Amplifier and High-Accuracy Quadrature Voltage-Controlled Oscillator

Design and analysis of a two-stage low-noise amplifier (LNA) and a bottom-series coupled quadrature voltage-controlled oscillator (QVCO) using a 65-nm CMOS dual-gate device are present in this paper. By using the proposed dual-gate device, the parasitic capacitance and the effective substrate resistance can be reduced. Moreover, the 3-dB cutoff frequency can be extended due to the reduction of the Miller effect. The bandwidth of the dual-gate LNA is investigated to compare with the conventional cascode configuration. Besides, the operation principle of the quadrature signal generation using the dual-gate device is also presented for the QVCO design. The two-stage dual-gate LNA demonstrates a flat 3-dB bandwidth of 7.3 GHz from 19.4 to 26.7 GHz and a maximum gain of 18.9 dB. At 24 GHz, the measured minimum noise figure is 4.7 dB, and the measured output third-order intercept point <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$({\rm OIP}_{3})$</tex></formula> is 11 dBm. The dual-gate QVCO exhibits an oscillation frequency of up to 25.3 GHz, a phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$-$</tex></formula> 109 dBc/Hz at 1-MHz offset frequency, an amplitude error of 0.16 dB, and a phase error of 0.8 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}$</tex></formula> . The proposed dual-gate CMOS device is very suitable for the linear and nonlinear circuit designs above 20 GHz, especially for millimeter-wave applications due to its high speed and compact area.

Wideband SAW-Less Receiver Front-End With Harmonic Rejection Mixer in 65-nm CMOS

A wideband direct-conversion receiver front-end featuring a new harmonic rejection technique is demonstrated in 65-nm CMOS. The circuit consists of a two-stage low-noise amplifier, the first stage with capacitive feedback, a harmonic rejection mixer using 25% and 50% duty cycle local oscillator signals, and a third-order channel-select filter with configurable bandwidth. The receiver front-end is intended for surface-acoustic-wave-less cellular applications, and its performance was measured at 900- and 1800-MHz bands. The average harmonic rejection over GSM and LTE channel bandwidths is between 60 and 70 dB. Peak harmonic rejection exceeds 80 dB. The noise figures (NFs) are 3.3 and 3.9 dB for the complete receiver front-end in low band and high band, respectively, with an S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> below -15 dB from 500 MHz to 2.5 GHz. The 1-dB received signal compression points with a blocker present at 20/80 MHz offset for low/high band are 0 and +2 dBm, respectively. The NF with 0-dBm blocker is 13 dB. For low band, the in-band IIP3 and IIP2 are -14.8 and > 49 dBm, respectively, and, for high band, -18.2 and > 44 dBm. The circuit worst case consumes 80 mW of power.

9-GHz Wideband CMOS RX and TX Front-Ends for Universal Radio Applications

Wideband receiver (RX) and transmitter (TX) RF front-ends for wireless universal radio applications are presented. The RX is comprised of a two-stage low-noise amplifier (LNA) applying feedback and shunt peaking, a combiner buffer for performance boosting, and an inverter-based in-phase/quadrature (IQ) down-conversion mixer. The wideband LNA provides input matching of better than -10 dB from dc to beyond 10 GHz. The conversion gain (CG) of the RX front-end has a peak value of 31 dB with a 3-dB bandwidth up to 9 GHz. The minimal noise figure is 6 dB and kept below 9 dB within the entire operational bandwidth. The RX has a linearity in terms of intermodulation distortion of better than -12 dBm. The direct conversion TX involving inverter-based IQ modulator and Darlington-type pre-power amplifier features operation up to 9 GHz with 10-dB mean CG and an average output power of 4 dBm at 1-dB compression level. Excluding buffers and local oscillator generation, the RX and TX dissipate 54 and 84 mW, respectively, from a 1.2-V voltage supply. The circuit prototypes have been fabricated in a standard 65-nm CMOS low-power process without any additional RF options and occupy an area of only 0.77 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.53 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , respectively.

Low-Power Sub-Harmonic Direct-Conversion Receiver With Tunable RF LNA and Wideband LO Generator at U-NII Bands

A low-power tunable-band sub-harmonic direct-conversion receiver covering the whole Unlicensed National Information Infrastructure band is demonstrated using 0.18-μm CMOS technology. The RF band is selected by tuning varactors at the loads of the two-stage low-noise amplifier, while a wideband octet- phase generator is applied at the local oscillator (LO) port. The band tuning of both an LC tank and a transformer and the de- sign of an optimal transformer turn ratio are fully discussed in this paper. Vertical-NPN bipolar junction transistors in a standard CMOS process are used at the mixer switching core for excellent 1/f noise performance. As a result, the receiver achieves a 48/50 voltage gain and 4.5/4.8-dB noise figure with a 1/f noise corner of 70 kHz when the RF band is tuned to 5.2/5.8 GHz, respectively. The dc current consumption of the RF front-end (including the LO buffer) is 8.5 mA at a 1.8-V supply.

A 1.7 2.5 GHz Active Inductor based Low Power Low Noise Amplifier for Multi Standard Applications

Due to an increasing demand for simultaneous global roaming and all-in-one wireless phones, the interest in the development of the multi-standard transceivers has been increased. In the receiver front end, the performance of Low Noise Amplifier (LNA) decides overall receiver sensitivity and hence its design plays a crucial role. In this paper, an active inductor based tunable two-stage LNA employing current reuse technique is proposed for multistandard applications. The LNA is aimed at supporting CDMA-2000, GSM, WCDMA, WiMAX, Bluetooth and UMTS-TDD in the bandwidth range of 1.7 – 2.5 GHz. The proposed LNA achieved a power gain of greater than 13 dB, noise figure less than 2 dB and impedance matching less than –8 dB for all the standards. The stability factor is maintained above 1, ensuring stable operation of the LNA without oscillations. The LNA consumes very low power of 7.96 mW at an operating voltage of 1V. The performance analysis of the proposed active inductor based tunable LNA is carried out using Agilent‟s ADS simulator employing 90 nm CMOS technology.

Design of variable gain low noise amplifier using feedback circuit with memory circuits for 5.2 GHz band

This paper presents a novel adaptive gain control method for Low Noise Amplifiers (LNAs) at the 5.2 GHz band using a feedback circuit, and operating in the baseband signal frequency. A uniform step variable gain can be implemented using a two-stage LNA based on the cascade topology. The feedback circuit consists of seven functional blocks, each of which has been designed for minimum power consumption. The storage circuit in the feedback circuit is used to store the previous signal magnitude, thus avoiding unnecessary power consumption in the LNA. We simulated the performances of LNA in terms of the gain, IIP3, Noise Figure (NF), stability, and power consumption. The adaptive front-end LNA with the feedback circuit can achieve a variable gain from 11.39 dB to 22.74 dB with excellent noise performance even at a high gain mode. The DC power of the proposed variable gain LNA consumes 5.68---6.75 mW under a 1.8 V supply voltage.

Low Noise Amplifier Design for Digital Television Applications

The DVB-T (Digital Video Broadcasting—Terrestrial) standard is being deployed in many parts of the world for digital broadcasting services, providing a variety of features extending the capabilities of the older analog ones. In this paper, a two-stage low noise amplifier (LNA) is designed for use with the DVB-T standard. The design is employed based on microstrip. The microwave design meets all the specifications required, achieving input and output return loss below ?10 dB, high gain of 35 dB and high linearity. Low noise figure of 1.3 dB is achieved with the use of pHEMT transistor technology.