Millimeter-Wave Low-Noise Amplifier Design in 28-nm Low-Power Digital CMOS

Abstract

This paper presents the design of a 60-GHz low-noise amplifier (LNA) in a 28-nm low-power (LP) bulk CMOS process. As the technology is optimized for digital LP applications, the design of millimeter-wave (mm-wave) circuits requires high-frequency design and modeling of all active and passive devices. This includes the development of a suitable RF-transistor layout, as well as transmission lines and high- $Q$ capacitors. The mm-wave circuit design aspects are further discussed with considerations about possible dc-distribution approaches, broadband matching networks, and optimum transistor loads. The proposed approach and device models have been validated with the fabrication and characterization of a two-stage 60-GHz LNA. This circuit exhibits 13.8 dB of power gain, 18 GHz of bandwidth, 4 dB of minimum noise figure, and an input referred 1-dB compression point at $-$ 12.5 dBm consuming 24 mW of dc power. Based on this performance and to the authors’ best knowledge, the presented amplifier shows the highest reported value for a commonly used figure-of-merit of 60-GHz LNAs.