Two-dimensional Process Simulation Research Articles

Temperature dependence of single-event transients in SiGe heterojunction bipolar transistors for cryogenic applications

We experimentally demonstrate that the dominant mechanism of single-event transients in silicon-germanium heterojunction bipolar transistors (SiGe HBTs) can change with decreasing temperature from +20 °C to −180 °C. This is accomplished by using a new well-designed cryogenic experimental system suitable for a pulsed-laser platform. Firstly, when the temperature drops from +20 °C to −140 °C, the increased carrier mobility drives a slight increase in transient amplitude. However, as the temperature decreases further below −140 °C, the carrier freeze-out brings about an inflection point, which means the transient amplitude will decrease at cryogenic temperatures. To better understand this result, we analytically calculate the ionization rates of various dopants at different temperatures based on Altermatt’s new incomplete ionization model. The parasitic resistivities with temperature on the charge-collection pathway are extracted by a two-dimensional (2D) TCAD process simulation. In addition, we investigate the impact of temperature on the novel electron-injection process from emitter to base under different bias conditions. The increase of the emitter–base junction’s barrier height at low temperatures could suppress this electron-injection phenomenon. We have also optimized the built-in voltage equations of a high current compact model (HICUM) by introducing the impact of incomplete ionization. The present results and methods could provide a new reference for effective evaluation of single-event effects in bipolar transistors and circuits at cryogenic temperatures, and could provide a new evidence of the potential of SiGe technology in applications in extreme cryogenic environments.

Optimized Design of the 100-V Silicon Based Power N-Channel LDMOS Transistor

In power integrated circuits (PICs), it is desirable to minimize the area of a power device region while maximizing its performances (i.e., higher breakdown voltage and lower on-resistance). Therefore, the area of a power device region mainly determines the total chip size and hence the cost. An optimized design of breakdown voltage and on-resistance in a power n-channel lateral-diffused MOSFET (nLDMOS) was investigated in this paper. Two-dimensional process and device simulators, such as the TSUPREM4 and Sentaurus EDA tools, will be used to predict the device characteristic behaviors. Eventually, it can be shown that a 100 V device will have an optimized breakdown voltage about 156.7 volts and onresistance Ron about 40.61 mΩ-cm2 under the Vgs-Vth= 5 V and LOCOS spacing d= 6 μm situations.

Two-Dimensional Chemical Etching Process Simulation for Printed Circuit Heat Exchanger Channels Based on Cellular Automata Model

ABSTRACTAs a new type of heat exchanger, the printed circuit heat exchanger (PCHE) with high compactness can work under high pressure and high temperature, and can be applied to the very high temperature gas nuclear reactors. The chemical etching technology is one of main processes during PCHE fabrication, which determines whether PCHE flow channels can be properly produced according to design. However, many factors can affect the etching quality and the poor etching process can cause a great deal of uncertainty on the precision of stainless steel flow channels. In this paper, a two-dimensional (2-D) cellular automata model (CA) is used to simulate the etching process on stainless steel to examine the change of channel features varying with time under certain etching rates. Moreover, the simulation results are compared with our previous experimental etching data. On the one hand, from the comparison of the simulation results with channels data by spray etching, 2-D CA model can realize the simulation of etching process and display channel features under different etching rates and lateral erosion rates in every time period. On the other hand, from the comparison of the simulation results with channels data by immersion etching under different FeCl3 concentration and etching liquid temperature, 2-D CA model vividly presents channel features under different factors, which can easily and clearly explain the influence of factors on the etching quality, puddling effect and so on. Therefore, the simulation result strengthens the understanding of the etching mechanism and is helpful to realize an efficient and precise PCHE fabrication.

Fast Marching Simulation of Two Dimensional Lithography Process of Thick Photoresists

Fast marching method is an accurate, extremely fast numerical technique in analyzing and computing moving fronts which can develop sharp corners and change topology. We successfully accomplish this method in two dimensions and the two-dimensional lithography process simulation of SU 8 photoresists has been implemented. The obtained results indicate that the fast marching method can actually accelerate the simulation and be used as an effective method for thick photoresist lithography process simulations.

Comparison between SOI nMOSFET's under Uniaxial and Biaxial Mechanical Stress in Analog Applications

This work presents a study comparing the analog performance of uniaxially and biaxially strained planar Silicon-on-Insulator nMOSFETs for a wide range of channel lengths. The study is performed via two-dimensional numerical and process simulation and supported by experimental measurements. The comparison between devices from the same technology with these two strained techniques demonstrated that higher intrinsic voltage gain is obtained for biaxial mechanical stress. However, the transconductance is higher for uniaxial mechanical stress for shorter devices (below 550 nm) leading to larger unity gain frequency. On the other hand, despite both strain techniques degrades the output conductance, this degradation with channel length shortening is less pronounced for devices under biaxial mechanical stress.

Analysis and Optimization of High-Voltage Devices in a BCD Process

: This paper presents two-dimensional process and device(15V) simulation results and optimization of power device in a 0.35um Bipolar/CMOS/DMOS(BCD) process. Detailed device simulations and structure designs have been done. Test structures with specific considerations have been developed. With both simulation and experimental results, the optimized devices show excellent performance, which have been demonstrated with characterization results from devices on wafers from process qualification lots.

A Novel Gate-Assisted Reverse-Read Scheme to Control Bit Coupling and Read Disturb for Multibit/Cell Operation in Deeply Scaled Split-Gate SONOS Flash EEPROM Cells

A dual-node split-gate silicon-oxide-nitride-oxide-silicon cell with a novel read scheme is proposed for 2-bit/cell operation. Using suitable gate screening bias in reverse read, bit coupling can be reduced, even when low read V D is used to keep read disturb under control. The proposed read scheme maintains the memory window for dual-bit/cell operation for deeply scaled cells. Two-dimensional process, device, and Monte Carlo simulations are extensively used to design and understand cell operation.

A High Performance 80V Smart LDMOS Power Device Based on Thin SOI Technology

The high junction leakages, circuit latched issues, and high parasite capacitances happened in junction isolation technology can be improved by the thin SOI (Silicon-On-Insulator) technology. A CMOS compatible SOI technology will be one of technologies used in the future roadmap of LDMOS devices. A CMOS compatible thin SOI LDMOS (Lateral Double-diffused MOSFET) device, with 0.18 micron gate length, 0.02 micron gate oxide and 3 micron N-drift region, is proposed to achieve the optimal (BVoff) off-state breakdown voltage and on-state resistance (Ron) values. The characteristics of the proposed LDMOS device are verified by the two-dimensional process simulator TSuprem-IV and the device simulator Medici. The simulated results have shown that a device performance at the range of BVoff, 80 v, and Ron, 190 mohm-mm2, is attended. The on-state breakdown voltage is measured at 70V with an excellent safe operating area (SOA) performance for the drain source current versus on-state breakdown voltage.

Linearity Analysis in Double Gate Graded-Channel Soi Devices Applied to 2-Mos Mosfet-C Balanced Structures

This paper examines the linearity of 2-MOS MOSFET-C balanced structures using conventional and Graded-Channel (GC) Gate-All-Around (GAA) devices. The distortion analysis has been performed through the evaluation of third order harmonic distortion (HD3). The study has been carried out through experimental results, two-dimensional process and device simulations. Along this work, the best operation bias in terms of HD3 is determined for each analysed device and the couple device that exhibits lower HD3 is pointed out. The use of GC GAA devices in 2-MOS structures has showed to improve the linearity in relation to the conventional GAA. Finally, a discussion over the non-linearities causes is performed clarifying their origins and the improvement provided by the adoption of GC GAA devices in 2-MOS structures.

Harmonic distortion analysis of double gate graded-channel MOSFETs operating in saturation

In this work we present an analysis of harmonic distortion (HD) in graded-channel (GC) gate-all-around (GAA) devices operating in saturation region for analog applications. The study has been performed through device characterization and two-dimensional process and device simulations. The overall study has been done on the total and third order HDs. When applied in the saturation regime as an amplifier, the GC outperforms conventional GAA transistors presenting simultaneously higher transconductance, lower drain output conductance and more than 15dB improved linearity. The influence of channel length reduction on the HD is also analyzed. Although slight linearity degradation is observed in both the conventional and the GC devices when reducing the channel length, the HD presented by the GC transistor is significantly lower than the one showed by conventional device for any studied channel length. This allows AC input signal amplitude up to 20 times higher than the conventional GAA for a same specified distortion level.

Channel Length Reduction Influence on Harmonic Distortion of Graded-Channel Gate-All-Around Devices

This work compares the linearity of conventional and Graded- Channel (GC) Gate-All-Around (GAA) devices for analog operation as in an amplifier when the channel length is scaled. The study has been performed through two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar bias the performance of GC GAA transistors remains better than the uniformly doped GAA for any channel length. Although scaling the devices tends to degrade the harmonic distortion, significant results were obtained for the GC configuration measured as an improvement of more than 15 dB in total harmonic distortion-to-gain ratio operating in the same region with channel length of 1μm and with lightly doped region length of 0.3 μm.

Application of Double Gate Graded-Channel SOI in MOSFET-C Balanced Structures

This work studies the linearity of conventional and Graded- Channel (GC) Gate-All-Around (GAA) devices when applied in 2- MOS and 4-MOS balanced structures operating as tunable resistors. The study has been performed through device characterization and two-dimensional process and device simulations. Total harmonic distortion (THD) and third order harmonic distortion (HD3) have been evaluated. When taking into account similar on-resistance, the use of the GC GAA transistors in both 2-MOS and 4-MOS structures improves the linearity. The use of GC GAA devices in 2-MOS balanced structures allows a reduction of the gate overdrive voltage of 22.5% without degrading THD and HD3. On the other hand, the use of GC GAA devices in 4-MOS structures leads to an improvement in both HD3 and THD by 7 dB for devices with similar channel length at the same gate voltage overdrive.

Exploratory study on power-efficient silicon nano-wire dynamic NMOSFET/PMESFET logic

The latest techniques in fabricating silicon-based, vertical surrounding gate MOSFETs (SGFET) instigate the pathway towards building the next generation ultra large-scale integration (ULSI). The study shows the design and optimisation of surrounding gate n-channel MOSFETs and p-channel MESFETs used in dynamic differential domino circuits suitable for an area-efficient technology. Three-dimensional device simulations investigate the maximum device transconductance and minimum OFF current of vertical, metal-gated nano-wire NMOSFETs and PMESFETs as a function of wire radius and doping concentration. Two-dimensional process simulations are carried out on the optimum transistor designs, and non-ideal device characteristics are measured. A family of differential dynamic circuits composed of a two-input AND (OR), and two-input XOR gates and a full adder are built to measure worst-case pre-charge and evaluate function delays, power dissipation and layout area.

에피층 농도 변화에 따른 Multi-RESURF SOI LDMOSFET의 전기적 특성 분석

In this paper, we analyzed the breakdown voltage and on-resistance of the multi-RESURF SOI LDMOSFET as a function of epi-layer concentration. P-/n-epi layer thickness and doping concentration of the proposed structure are varied from <TEX>$2{\sim}5{\mu}m\;and\;1\{times}10^{15}/cm^{3}^{\sim}9\{times}10^{15}/cm^{3}$</TEX> to find optimum breakdown voltage and on-resistance of the proposed structure. The maximum breakdown voltage of the proposed structure is <TEX>$224\;V\;at\;R_{on}=0.2{\Omega}-mon^{2}\;with\;P_{epi}=3\{times}10^{15}/cm^{3},\;N_{epi}=7\{times}10^{15}/cm^{3}\;and\;L_{epi}=10{\mu}m$</TEX>. Characteristics of the device are verified by two-dimensional process simulator ATHENA and device simulator ATLAS.

The design and analysis of dynamic NMOSFET/PMESFET logic using silicon nano-wire technology

A complete study including process flow, device design and circuit design issues is conducted to investigate the possibility of using surrounding gate NMOSFETs and PMESFETs for an area-efficient technology. Three-dimensional device simulations are performed to analyse the maximum current drive capacity and OFF current of vertical, metal-gated nano-wire NMOSFETs and PMESFETs as a function of wire radius and doping concentration. Two-dimensional process simulations are conducted on the optimum transistor designs and non-ideal I–V characteristics of the processed NMOSFET and PMESFET were measured and compared against the ideal characteristics. Various differential dynamic circuits including full adder, 2-input AND (OR) and XOR gates are built to measure transient performance, power dissipation and layout area based on the selected FET designs.

Enhanced Breakdown Voltage, Diminished Quasi-Saturation, and Self-Heating Effects in SOI Thin-Film Bipolar Transistors for Improved Reliability: A TCAD Simulation Study

Based on an extensive two-dimensional process and device simulation studies, a new n/sup +/-p-n-n/sup +/ vertical submicrometer bipolar junction transistor with a three-zone step doped lateral collector (VSLC) structure is presented. It is demonstrated for the first time that the breakdown voltage of the thin-film (<0.5 /spl mu/m) bipolar transistors can be enhanced significantly by using a combination of a vertical thin base and the VSLC structure. The proposed VSLC structure exhibits: 1) excellent output characteristics; 2) diminished quasi-saturation; 3) improved reliability against self-heating effect; and 4) enhanced breakdown voltage as high as 60% more than that of the conventional thin-film lateral bipolar transistor (LBT) on silicon-on-insulator. It also obviates the difficulties associated with the formation of a thin base in LBTs.

A New High Breakdown Voltage Lateral Schottky Collector Bipolar Transistor on SOI: Design and Analysis

Using two-dimensional process and device simulation, we present for the first time, a new high breakdown voltage two-zone base extended buried oxide (BOX) lateral Schottky Collector Bipolar Transistor (SCBT) on silicon-on-insulator with a breakdown voltage as high as 12 times that of the conventional lateral Schottky collector bipolar transistor. We have explained the new design features of the proposed Schottky collector structure and the reasons for its significantly improved breakdown performance. The proposed structure is expected to be suitable in the design of the new generation scaled high voltage Schottky collector bipolar transistors for low power high speed analog applications.

Process and Device Simulation of a SiC Floating Junction Schottky Barrier Diode (Super-SBD)

This paper describes process and device simulation results of SiC floating junction Schottky barrier diodes (Super-SBDs). Two-dimensional process simulation of a SiC device is implemented using the customized ISE’s process simulator “DIOS”. The simulation results reproduce the experimentally observed buried floating junction structure of a SiC Super-SBD. The device simulation method using the anisotropic impact ionization coefficients is formulated. The effect of anisotropic avalanche breakdown field on termination structures of SiC SBDs is examined. Finally, by the device simulation we have shown that the trade-off between the on-state resistance and the breakdown voltage of the super-SBD that contains two drift layers exceeds that of the conventional SBD.

Surface Accumulation Layer Transistor (SALTran): A New Bipolar Transistor for Enhanced Current Gain and Reduced Hot-Carrier Degradation

We report a new surface accumulation layer transistor (SALTran) on SOI which uses the concept of surface accumulation of electrons near the emitter contact to improve the current gain significantly. Using two-dimensional process and device simulation, the performance of the proposed device has been evaluated in detail by comparing its characteristics with those of the previously published conventional bipolar transistor structure. From our simulation results, it is observed that depending on the choice of emitter doping and emitter length, the proposed SALTran exhibits a current gain enhancement of 10 to 70 times that of the compatible bipolar transistor. We also demonstrate that the presence of the surface accumulation layer does not deteriorate the cut-off frequency as observed in the high-low emitter junction bipolar transistors. Our simulations also indicate that when the emitter is lightly doped, the SALTran is immune to hot carrier injection problems due to the reduced electric field in the emitter. The effect of surface states at the emitter contact and temperature on current gain have been examined.

Fabrication and Process Simulation of SOI MOSFETs with a 30-nm Gate Length

We have obtained systematic simulation and experimental results for 30-nm-gate-length metaloxide-semiconductor field-effect transistor (MOSFET) fabricated on ultra-thin silicon-on-insulator (SOI) substrates. The two-dimensional process simulation and the device simulation were carried out to optimize the fabrication process conditions and the device characteristics of 30-nm-gatelength SOI MOSFETs. A new simple source/drain formation technique using the solid-phase diffusion (SPD) method was developed. Based on the simulation results and the SPD ultra-shallow junction formation technique, we successfully fabricated 30-nm-gate-length SOI nMOSFETs. The experimental results for the 30-nm-gate-length SOI nMOSFETs showed good transistor behaviors and superior device scalability.