A High Performance 80V Smart LDMOS Power Device Based on Thin SOI Technology

Abstract

The high junction leakages, circuit latched issues, and high parasite capacitances happened in junction isolation technology can be improved by the thin SOI (Silicon-On-Insulator) technology. A CMOS compatible SOI technology will be one of technologies used in the future roadmap of LDMOS devices. A CMOS compatible thin SOI LDMOS (Lateral Double-diffused MOSFET) device, with 0.18 micron gate length, 0.02 micron gate oxide and 3 micron N-drift region, is proposed to achieve the optimal (BVoff) off-state breakdown voltage and on-state resistance (Ron) values. The characteristics of the proposed LDMOS device are verified by the two-dimensional process simulator TSuprem-IV and the device simulator Medici. The simulated results have shown that a device performance at the range of BVoff, 80 v, and Ron, 190 mohm-mm2, is attended. The on-state breakdown voltage is measured at 70V with an excellent safe operating area (SOA) performance for the drain source current versus on-state breakdown voltage.