Abstract
A complete study including process flow, device design and circuit design issues is conducted to investigate the possibility of using surrounding gate NMOSFETs and PMESFETs for an area-efficient technology. Three-dimensional device simulations are performed to analyse the maximum current drive capacity and OFF current of vertical, metal-gated nano-wire NMOSFETs and PMESFETs as a function of wire radius and doping concentration. Two-dimensional process simulations are conducted on the optimum transistor designs and non-ideal I–V characteristics of the processed NMOSFET and PMESFET were measured and compared against the ideal characteristics. Various differential dynamic circuits including full adder, 2-input AND (OR) and XOR gates are built to measure transient performance, power dissipation and layout area based on the selected FET designs.
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