Static NMOS circuits for crossbar architectures using silicon nano-wire technology

Abstract

This study shows the design and analysis of static NMOS gates composed of silicon nano-wire surrounding gate pull-down NMOSFETs (SGFETs) and p-type pull-up resistors as the primary building blocks to form high density circuits. The device geometry and doping concentration of NMOS transistors and p-type resistors are varied until the lowest noise margin and standby power dissipation are obtained for an inverter. The optimum NMOS transistor and p-type resistor configurations are subsequently used to build various NOR-type static logic gates including a full adder to evaluate the transient performance, power consumption and layout area of each gate. A power-saving technique that replaces the p-type pull-up resistor with a p-type MESFET is also investigated for large-scale logic strings. Simulation results indicate that the worst-case rise and fall delays for a full adder are 130 ps and 90 ps at no capacitive load, and increase by 27.5 ps and 10 ps per fan-out, respectively. The worst-case power dissipation for the same circuit is 186.4 µW. The full adder circuit occupies approximately a 25 μm2 area if laid out conventionally and 36 µm2 if laid out on a crossbar platform. Compared to same feature size conventional CMOS technologies, silicon nano-wire technology offers simplicity in interconnect routing and reduction in the layout area for similar circuit performance.