Twiddle Factors Research Articles

An area-efficient and low-power 64-point pipeline Fast Fourier Transform for OFDM applications

In an orthogonal frequency division multiplexing (OFDM) based wireless systems, Fast Fourier Transform (FFT) is a critical block as it occupies large area and consumes more power. In this paper, we present an area-efficient and low power 16-bit word-width 64-point radix-22 and radix-23 pipelined FFT architectures for an OFDM-based IEEE 802.11a wireless LAN baseband. The designs are derived from radix-2k algorithm and adopt a Single-Path Delay Feedback (SDF) architecture for hardware implementation. To eliminate the complex multipliers and read-only memory (ROM) which is used for internal storage of twiddle factor coefficients, the proposed 64-point FFT employs a Canonical Signed Digit (CSD) complex constant multiplier using adders, multiplexers and shifters. The complex constant multiplier (CCM) is modified using common sub-expression sharing block that reduces the area of the design. The proposed radix-22 and radix-23 pipelined FFT architectures are modeled and implemented using TSMC 180nm CMOS technology with a supply voltage of 1.8V. The implementation results show that the proposed architectures significantly reduces the hardware cost and power consumption in comparison to existing 64-point FFT architectures.

2048-Point Fast Fourier Transform Processing Based on Twiddle Factor Reduction and Dynamic Data Scaling

2048-Point Fast Fourier Transform Processing Based on Twiddle Factor Reduction and Dynamic Data Scaling

Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units

Split-radix fast Fourier transform (SRFFT) is an ideal candidate for the implementation of a low-power FFT processor, because it has the lowest number of arithmetic operations among all the FFT algorithms. In the design of such processors, an efficient addressing scheme for FFT data as well as twiddle factors is required. The signal flow graph of SRFFT is the same as radix-2 FFT, and therefore, the conventional address generation schemes of FFT data could also be applied to SRFFT. However, SRFFT has irregular locations of twiddle factors and forbids the application of radix-2 address generation methods. This brief presents a shared-memory low-power SRFFT processor architecture. We show that SRFFT can be computed by using a modified radix-2 butterfly unit. The butterfly unit exploits the multiplier-gating technique to save dynamic power at the expense of using more hardware resources. In addition, two novel address generation algorithms for both the trivial and nontrivial twiddle factors are developed. Simulation results show that compared with the conventional radix-2 shared-memory implementations, the proposed design achieves over 20% lower power consumption when computing a 1024-point complex-valued transform.

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage

The fast Fourier transform (FFT) is perhaps today’s most ubiquitous algorithm used with digital data; hence, it is still being studied extensively. Besides the benefit of reducing the arithmetic count in the FFT algorithm, memory references and scheme’s projection on processor’s architecture are critical for a fast and efficient implementation. One of the main bottlenecks is in the long latency memory accesses to butterflies’ legs and in the redundant references to twiddle factors. In this paper, we describe a new FFT implementation on high-end very long instruction word (VLIW) digital signal processors (DSP), which presents improved performance in terms of clock cycles due to the resulting low-level resource balance and to the reduced memory accesses of twiddle factors. The method introduces a tradeoff parameter between accuracy and speed. Additionally, we suggest a cache-efficient implementation methodology for the FFT, dependently on the provided VLIW hardware resources and cache structure. Experimental results on a TI VLIW DSP show that our method reduces the number of clock cycles by an average of 51 % (2 times acceleration) when compared to the most assembly-optimized and vendor-tuned FFT libraries. The FFT was generated using an instruction-level scheduling heuristic. It is a modulo-based register-sensitive scheduling algorithm, which is able to compute an aggressively efficient sequence of VLIW instructions for the FFT, maximizing the parallelism rate and minimizing clock cycles and register usage.

Efficient Implementation of Radix-4 Single pathDelay Feedback (SDF) FFT ProcessorsK

The aim of the current research work is to improve the digital architecture (Radix-4 Single path Delay Feedback) of frequency transformation process. Radix-4 structure reduces the number of steps to half than Radix-2 structure. In the proposed Radix-4 SDF FFT architecture, sequential structures are designed with the help of flip-flops. Traditional FFT structure has complex multiplier architecture to perform the twiddle factor multiplication. But it is not sufficient to large point FFT calculation. Hence, to overcome this problem, Bit Parallel Multiplication (BPM) has been introduced in this paper. In addition, data flow complexity of BPM structures have been realized and re-designed by reducing the most complexity paths. Proposed BPM based twiddle factor multiplier offers 17.5% improvements in area utilization and 7.22% improvements in latency for the value 0.707 and 15.3% improvements in area utilization and 5.97% improvements in latency for the value 0.9238. Proposed Radix-4 SDF FFT offers 47.96% improvements of total latency in Virtex E and 28.02% improvements of total latency in Virtex 6 than traditional Radix-2 SDF FFT. Power consumption of Proposed Radix-4 SDF FFT offers 69.69% improvements in Virtex E and 14.95% improvements in Virtex 6 than traditional Radix-2 SDF FFT. In future, proposed BPM based twiddle factor multiplier will be useful in Orthogonal Frequency Division Multiplexing (OFDM) and Software Defined Radio (SDR) for performing data communication process efficiently.

A low-area dynamic reconfigurable MDC FFT processor design

Fast Fourier Transform (FFT) is widely utilized to perform data computation in orthogonal frequency-division multiplexing (OFDM) systems. Wireless networks use 64-point to 512-point FFT to implement task. However, different FFT protocols have different lengths. Building all required points into circuits independently leads to a massive hardware resource requirement. To minimize the hardware resource requirement, Partial dynamic reconfiguration (PDR) FPGA can be adopted to build FFT modules and switched using time-independent circuits, which increasing the system design flexibility. The proposed FFT processor uses 64-point FFT on a static circuit, with other points configured as reconfigurable modules (RMs). The system can configure 64 to 512 points under different environment, and using PDR also reduced the occupied hardware resources. This work presents a four-path Multipath Delay Commutator (MDC), which can increase the FFT processor throughput. The twiddle factor (T.F.) computational circuits in FFT can be implemented with a right shift and adder circuits to calculate the fixed-point format to minimize the design complexity. Experimental results illustrate that the proposed design can increase the throughput of FFT processor, and reduce the number of FPGA slices by up to 76.6% at 256-point FFT, and the flip-flop by up to 58.9% at 64-point FFT.

Efficient Design of Bit Parallel Multiplication based Radix-4 Multipath Delay Commutator (R4mdc) FFT

This paper presents the Fast Fourier Transform (FFT) techniques for converting a signal in the time domain to the frequency domain. The advent of Fast Fourier Transform (FFT) method has greatly extended our ability to implement the Fourier methods on digital computers. FFT is an algorithm that speeds up the calculation of Discrete Fourier Transform (DFT). Pipelined FFT have features like simplicity, modularity and high throughput. Radix-2 Multi-Path Delay Commutator (R2MDC) FFT is the best frequency transformation architecture for FFT calculation. However it requires more delay elements to provide desired frequency transformation functions. To overcome this problem, Radix-4 Multi-Path Delay Commutator (R4MDC) has been designed in this paper. In addition, structure of Bit Parallel Multiplication (BPM) has been modified to alleviate the performance of twiddle factor multiplier of FFT architecture. Modified BPM structure has utilized only little hardware to perform the twiddle factor multiplication. Finally, Modified BPM structures have been incorporated into R4MDC FFT structure for alleviating the performances of frequency transformation process. Design of proposed methods has been validated by using ModelSim 6.3C and Synthesis results has been evaluated by using Xilinx 12.4i (Family: Spartan 3, Device: Xc3s200, Package: PQ208, Speed: -5) design tool.

A New Representation of FFT Algorithms Using Triangular Matrices

In this paper we propose a new representation for FFT algorithms called the triangular matrix representation. This representation is more general than the binary tree representation and, therefore, it introduces new FFT algorithms that were not discovered before. Furthermore, the new representation has the advantage that it is simple and easy to understand, as each FFT algorithm only consists of a triangular matrix. Besides, the new representation allows for obtaining the exact twiddle factor values in the FFT flow graph easily. This facilitates the design of FFT hardware architectures. As a result, the triangular matrix representation is an excellent alternative to represent FFT algorithms and it opens new possibilities in the exploration and understanding of the FFT.

A High-Throughput Low-Complexity Radix-<inline-formula> <tex-math notation="LaTeX">$2^{\textbf {4}}$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$2^{\textbf {2}}$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$2^{\textbf {3}}$ </tex-math></inline-formula> FFT/IFFT Processor With Parallel and Normal Input/Output Order for IEEE 802.11ad Systems

This brief presents a high-throughput low-complexity 512-point fast Fourier transform (FFT)/inverse fast Fourier transform (IFFT) processor for IEEE 802.11ad standard aiming at the wireless personal area network applications. To reduce the complexity of twiddle factor multiplication, the radix- $\boldsymbol {2^{4}}$ - $\boldsymbol {2^{2}}$ - $\boldsymbol {2^{3}}$ FFT algorithm is devised. To achieve the throughput of 1.76 GS/s (which is normalized as eight samples/clock) and meet the frame format of single carrier as well as orthogonal frequency division multiplexing physical layer that no interval is inserted between any two 512-length data blocks in a frame, the mixed-radix multipath delay feedback structure is adopted to support the continuous data flow. Moreover, we propose a novel reorder scheme to support parallel normal-order output data flow continuously, which demands only a single-RAM-group, i.e., 512-word memory size with very simple control logic. Overall, the whole FFT/IFFT processor is high throughput and area efficient, and the back-end simulation results show that the core area of the FFT processor is 1.69 $\mathrm{mm}^{2}$ in Silterra 0.13 ${\mu }$ m process.

Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip

This paper reports the design and development of reconfigurable (up to 8192-point), data parallel, constant geometry fast Fourier transform (CG-FFT) architectures based on Network-on-Chip (NoC) paradigm. Twiddle factor multiplications have been realized using pipelined CORDIC rotators in the proposed architecture in order to ensure its high throughput. Mapping of FFT functions to cores has been done by considering the proposed signal flow graph (SFG) for CG-FFT architecture, which helps in optimizing the design of network components (routers and network interfaces) and reducing the latency of FFT computation. The proposed input-size aware architecture can withstand faults in other processing elements (PEs) as it can accomplish the entire FFT computation using only one PE as well. When mapped onto mesh based NoC, the proposed architectures could achieve reduction in latency by 5×, compared to several existing FFT architectures on NoC. Hardware realization of the PE and the network components of the proposed architectures have been done using Xilinx Kintex-7 family field-programmable gate array (FPGA) device. The maximum operating frequency of a PE in the proposed architecture has been found to be 184.010 MHz, which meets the timing specifications of several application standards, such as DVB-T/H, DAB, 802.11a/n and UWB. In addition to the FPGA-prototype, the proposed architectures have also been synthesized in ASIC design flow to obtain area and power results.

VLSI Implementation of Reconfigurable FFT Processor Using Vedic Mathematics

Fast Fourier transform has been used in wide range of applications such as digital signal processing and wireless communications. In this we present a implementation of reconfigurable FFT processor using single path delay feedback architecture. To eliminate the use of read only memory’s (ROM’S). These are used to store the twiddle factors. To achieve the ROM-less FFT processor the proposed architecture applies the bit parallel multipliers and reconfigurable complex multipliers, thus consuming less power. The proposed architecture, Reconfigurable FFT processor based on Vedic mathematics is designed, simulated and implemented using VIRTEX-5 FPGA. Urdhva Triyakbhyam algorithm is an ancient Vedic mathematic sutra, which is used to achieve the high performance. This reconfigurable DIF-FFT is having the high speed and small area as compared with other conventional DIF-FFT

A New Relation between “Twiddle Factors” in the Fast Fourier Transformation

The fast Fourier transformation algorithm (FFT) probably is the most important algorithm in the digital signal processing. It is an efficient algorithm to the discrete Fourier transformation which determines the frequency components of a discrete time-varying signal. Nowadays, it has a huge impact on the modern society because the FFT is running on more billion devices (e.g. smartphones) on the planet all the time and this tendency is continuously increasing. Moreover, this algorithm plays a key role in the computer science and engineering. Consequently, a well optimized algorithm can save tremendous resources (calculation capacity and memory). This paper presents a new relation between “twiddle factors” and gives an optimised form to the existing relations. In the paper the experimental results prove the efficiency of the proposed relations. By the new relations every radix-r and split-radix FFT will be more efficient because it accelerates the algorithm and/or saves memory. DOI: http://dx.doi.org/10.5755/j01.eee.21.4.12784

VLSI Implementation and Area EfficientCordic based Integer DCT Architectures forHEVC

In signal progressing domain, recent days there is bottleneck parameter performance like area, latency. To provide area efficient integer Discrete Cosine Transform (DCT) designs for High Efficiency Video Coding (HEVC). So that invoked CORDIC architecture to produce on fly trigonometric output instead of traditional method. In integer DCT have its own style of operation and to calculate twiddle factor of DCT CORDIC architecture actively introduced and make sustainable result in area. The computational complexity has been reduced considerably half as compare to traditional operations. The Experimental result shows that the proposed Dct algorithm has not only reduces the computational complexity. Significantly, it also keeps the better transformation quality of the efficient integer DCT. Therefore, the proposed CORDIC based integer DCT can be used in area efficient and high speed HEVC systems especially in battery-based systems. The design has been verified using Modelsim 6.4se and obtain RTL schematic using Xilinx 13.1 Ise.

High-Precision, Permanently Stable, Modulated Hopping Discrete Fourier Transform

A new modulated hopping Discrete Fourier Transform (mHDFT) algorithm which is characterized by its merits of high accuracy and constant stability is presented. The proposed algorithm, which is based on the circular frequency shift property of DFT, directly moves the k-th DFT bin to the position of k = 0, and computes the DFT by incorporating the successive DFT outputs with arbitrary time hop L. Compared to previous works, since the pole of mHDFT precisely settles on the unit circle in the Z-plane, the accumulated errors and potential instabilities, which are caused by the quantization of the twiddle factor, are always eliminated without increasing much computational effort. The numerical simulation results verify the effectiveness and superiority of the proposed algorithm.

Datapath-regular implementation and scaled technique for N=3×2m DFTs

Discrete Fourier transform (DFT) is used widely in almost all fields of science and engineering, and is generally calculated using the fast Fourier transform (FFT) algorithm. In this paper, we present a fast algorithm for efficiently computing a DFT of size 3×2m. The proposed algorithm decomposes the DFT, obtaining one length-2m unscaled sub-DFT and two length-2m sub-DFTs scaled by constant real numbers. For efficiently computing the scaled sub-DFTs, the constant real factors are attached to twiddle factors, combining them into new twiddle factors. By using this approach, the number of real multiplications is reduced compared with existing algorithms. To obtain regular datapath, a novel implementation method is presented aiming at the implementation of the proposed algorithm and making its datapath regular like the radix-2 FFT algorithm. The method can be applied to other algorithms with L-shape butterfly. Experimental result shows that, the proposed algorithm consumes less processing time than the existing algorithms for all scale DFTs, and than FFTW, a C subroutine library of FFTs, just for small scale DFTs.

A New Method of Doppler Frequency and DOA Estimation Based on Gradient-Time-Delay

This paper proposes that arrays of spatio-temporal data matrix was constructed by the arrays of the received signal delayed in time gradient, Meanwhile, applying the method of ESPIRT to get the twiddle factor of the received signal array element and the array element of the time and the space, finally get the final information of Doppler frequency and the information of arrival angle though applying least squares method.

Low power reconfigurable FP-FFT core with an array of folded DA butterflies

A variable length (32 ~ 2,048), low power, floating point fast Fourier transform (FP-FFT) processor is designed and implemented using energy-efficient butterfly elements. The butterfly elements are implemented using distributed arithmetic (DA) algorithm that eliminates the power-consuming complex multipliers. The FFT computations are scheduled in a quasi-parallel mode with an array of 16 butterflies. The nodes of the data flow graph (DFG) of the FFT are folded to these 16 butterflies for any value of N by the control unit. Register minimization is also applied after folding to decrease the number of scratch pad registers to (log 2 N − 1) × 16. The real and imaginary parts of the samples are represented by 32-bit single-precision floating point notation to achieve high precision in the results. Thus, each sample is represented using 64 bits. Twiddle factor ROM size is reduced by 25% using the symmetry of the twiddle factors. Reconfigurability based on the sample size is achieved by the control unit. This distributed floating point arithmetic (DFPA)-based design of FFT processor implemented in 45-nm process occupies an area of 0.973 mm2 and dissipates a power of 68 mW at an operating frequency of 100 MHz. When compared with FFT processor designed in the same technology with multiplier-based butterflies, this design shows 33% less area and 38% less power. The throughput for 2,048-point FFT is 222 KS/s and the energy spent per FFT is 7.4 to 14 nJ for 64 to 2,048 points being one among the most energy-efficient FFT processors.

Low Power 128 Point Split Radix FFT for LTE Application

In this paper, we describe a processor architecture customized to Split radix FFT algorithm. The proposed architecture supports all FFT sizes, required by the LTE applications. The proposed design is aimed to reduce the area, latency, power and also to reduce the number of computational path in order to speed up FFT processor computation. The proposed low power 128 point split radix FFT architecture applies various periodicity properties of twiddle factors multiplier.We implement the processor in 128-point MDC architecture with split radix algorithm. The processor has been synthesized on a Xilinx ISE 10.1design technology and both energy-efficiency and performance have been evaluated.

Constant twiddle factor multiplier sharing in multipath delay feedback parallel pipelined FFT processors

A new constant twiddle factor multiplier sharing method in parallel pipelined fast Fourier transform (FFT) processors based on a multi-path delay feedback architecture which consists of multiple single-path delay feedback datapaths is presented. The proposed method exploits constant twiddle factor multiplier relocation which moves a constant twiddle factor multiplier into a feedback path based on twiddle factor decomposition. By relocating a twiddle factor multiplier, the timing of twiddle factor multiplications is changed so that the multiplications with a twiddle factor are performed at different clock cycles in two datapaths, which makes it possible that the two datapaths share a multiplier operating with the twiddle factor. A reduction of 50% in the number of constant twiddle factor multipliers in the first two stages of a 128-point four-parallel pipelined FFT processor is achieved using the proposed method.

Design and Implementation of 1-D and 2-D Mixed Architecture FFT Processor in Heterogeneous Multi-core SoC based on FPGA

A novel architecture FFT processor which can carry on 1-D FFT algorithm or 2-D FFT algorithm corresponding different size of FFT is proposed in this paper. The architecture is served as a scalable IP Core which is suitable for the heterogeneous multi-core SoC on chip application. The mixed architecture FFT processor achieves balance between high processing speed and resources. Compared with a conventional 1-D FFT processor, this FFT processor is characterized by having smaller resources consumption; compared with a 2-D FFT processor which is mapped onto a long point FFT architecture, it has higher processing speed. It employs the Radix-2 DIT-FFT algorithm and fixed addressing structure. It takes two ways to hide time consumed on data-path, one is read-ahead operation of dual-port RAM to hide the delay introduced by 12-stages pipeline of butterfly-unit and Memory access delay; the other is Ping-Pong operation of 3 groups of RAM to conceal data transmitting time. It also adopt twiddle factor compression algorithm to reduce ROM space. It can carry out 2 n (n is from range of 5 to 14) single-precision floating-point FFT/IFFT directly. As a result, we have implemented the mixed architecture FFT processor based on FPGA, and successfully applied it into the heterogeneous multi-core SoC.