A low-area dynamic reconfigurable MDC FFT processor design

Abstract

Fast Fourier Transform (FFT) is widely utilized to perform data computation in orthogonal frequency-division multiplexing (OFDM) systems. Wireless networks use 64-point to 512-point FFT to implement task. However, different FFT protocols have different lengths. Building all required points into circuits independently leads to a massive hardware resource requirement. To minimize the hardware resource requirement, Partial dynamic reconfiguration (PDR) FPGA can be adopted to build FFT modules and switched using time-independent circuits, which increasing the system design flexibility. The proposed FFT processor uses 64-point FFT on a static circuit, with other points configured as reconfigurable modules (RMs). The system can configure 64 to 512 points under different environment, and using PDR also reduced the occupied hardware resources. This work presents a four-path Multipath Delay Commutator (MDC), which can increase the FFT processor throughput. The twiddle factor (T.F.) computational circuits in FFT can be implemented with a right shift and adder circuits to calculate the fixed-point format to minimize the design complexity. Experimental results illustrate that the proposed design can increase the throughput of FFT processor, and reduce the number of FPGA slices by up to 76.6% at 256-point FFT, and the flip-flop by up to 58.9% at 64-point FFT.