Reconfigurable data parallel constant geometry fast Fourier transform architectures on Network-on-Chip

Abstract

This paper reports the design and development of reconfigurable (up to 8192-point), data parallel, constant geometry fast Fourier transform (CG-FFT) architectures based on Network-on-Chip (NoC) paradigm. Twiddle factor multiplications have been realized using pipelined CORDIC rotators in the proposed architecture in order to ensure its high throughput. Mapping of FFT functions to cores has been done by considering the proposed signal flow graph (SFG) for CG-FFT architecture, which helps in optimizing the design of network components (routers and network interfaces) and reducing the latency of FFT computation. The proposed input-size aware architecture can withstand faults in other processing elements (PEs) as it can accomplish the entire FFT computation using only one PE as well. When mapped onto mesh based NoC, the proposed architectures could achieve reduction in latency by 5×, compared to several existing FFT architectures on NoC. Hardware realization of the PE and the network components of the proposed architectures have been done using Xilinx Kintex-7 family field-programmable gate array (FPGA) device. The maximum operating frequency of a PE in the proposed architecture has been found to be 184.010 MHz, which meets the timing specifications of several application standards, such as DVB-T/H, DAB, 802.11a/n and UWB. In addition to the FPGA-prototype, the proposed architectures have also been synthesized in ASIC design flow to obtain area and power results.