A High-Throughput Low-Complexity Radix-<inline-formula> <tex-math notation="LaTeX">$2^{\textbf {4}}$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$2^{\textbf {2}}$ </tex-math></inline-formula>-<inline-formula> <tex-math notation="LaTeX">$2^{\textbf {3}}$ </tex-math></inline-formula> FFT/IFFT Processor With Parallel and Normal Input/Output Order for IEEE 802.11ad Systems

Abstract

This brief presents a high-throughput low-complexity 512-point fast Fourier transform (FFT)/inverse fast Fourier transform (IFFT) processor for IEEE 802.11ad standard aiming at the wireless personal area network applications. To reduce the complexity of twiddle factor multiplication, the radix- $\boldsymbol {2^{4}}$ - $\boldsymbol {2^{2}}$ - $\boldsymbol {2^{3}}$ FFT algorithm is devised. To achieve the throughput of 1.76 GS/s (which is normalized as eight samples/clock) and meet the frame format of single carrier as well as orthogonal frequency division multiplexing physical layer that no interval is inserted between any two 512-length data blocks in a frame, the mixed-radix multipath delay feedback structure is adopted to support the continuous data flow. Moreover, we propose a novel reorder scheme to support parallel normal-order output data flow continuously, which demands only a single-RAM-group, i.e., 512-word memory size with very simple control logic. Overall, the whole FFT/IFFT processor is high throughput and area efficient, and the back-end simulation results show that the core area of the FFT processor is 1.69 $\mathrm{mm}^{2}$ in Silterra 0.13 ${\mu }$ m process.