Turn-off Energy Loss Research Articles

A fast-switching and short-circuit enhanced SOI LIGBT with a Self-Driving P-MOS

A fast-switching and short-circuit enhanced LIGBT with integrated Self-Driving P-channel MOS, named SDP-LIGBT is demonstrated by the TCAD SENTAURUS. The SDP consists of P + Emitter (Drain), N-type Carrier Store (N-CS Substrate) and P-shield (Source), and the gate of the SDP (PG) is shortly connected with the P + Emitter, thus the VPG,S equals VDS. Consequently, the SDP can be triggered on with saturate state without extra control signal. At the forward conduction, the SDP is automatically turned on with the increased VCE, then the saturation current is remarkably decreased due to division of LIGBT part and SDP part. Moreover, the N-CS substrate of the SDP acts as the hole barrier, which further decreased the on-state voltage drop (VON). At the turn-off process, the SDP is also automatically turned on to extract excessive carriers with the increased bus voltage VCE, thus the turn-off speed and turn-off energy loss (EOFF) is effectively reduced. As a result, the SDP-LIGBT achieves superior trade-off relationship between VON and EOFF. Furthermore, the short-circuit property of SDP-LIGBT is also significantly enhanced.

Actual Reasons Involving Turn-Off Losses Improvement With Increasing Load and Gate Resistance in MOSFETs Enhanced With Kelvin Source

This paper explains the actual reasons behind the improvement in terms of turn-off energy losses (Eoff) reduction, obtained using Kelvin pin (4-lead, 4L) MOSFETs instead of 3L ones. Eoff increases by increasing gate resistance and load, but the experimental results reveal that the increment is less in 4L than in 3L MOSFETs. Analysing the turn-off waveforms and adopting circuit analysis, the paper first proves that the common argument about the undesired effect of the parasitic source inductance in 3L MOSFETs is misleading. Then, the reasons behind the aforesaid improvement in 4L MOSFETs with increasing gate resistance and load are described by means of the derived analytical expressions. Finally, the analysis of the equations has provided helpful information at the design stage, also accounting for the different device technologies. In particular, the improvement obtained using 4L MOSFETs reduces as the driving loop parasitic inductance increases and evanesces if its value becomes comparable with the power loop parasitic inductance.

Numerical analysis of an ultralow switching loss IGBT with super junction and blocking junction

In order to reduce the switching loss (ESW) and enhance the breakdown voltage (BV), in this paper, an insulated gate bipolar transistor with an internal blocking junction and super junction (SJBJ-IGBT) is proposed and investigated. By inserting P-pillar and N-pillar on both sides of the drift region, a drift area with auxiliary depletion function can be formed. The junction of the primary blocking layer (JPB) is located internally in the device’s drift region. The JPB is reverse biased and withstand the main E-field during device turn-off. Meanwhile, the JPB is surrounded by P-pillar and N-pillar, reducing the E-field(E-field) peak value of device, and making E-field distribution more uniform. Furthermore, during device turn-on, the reduction of the effective area of drift region makes it easier for the JPB side of the P-drift region to accumulate excess holes. So that the SJBJ-IGBT is easier to turn-on. The snapback phenomenon of SJBJ-IGBT is eliminated. Simulation results demonstrate that, under the same forward conduction voltage (VON) condition, the proposed device exhibits a significantly lower turn-on energy loss (EON) compared to the traditional super junction(SJ-IGBT), and is 44.5% lower than that of IPBJ-IGBT, while their turn-off energy losses (EOFF) are almost equivalent.Besides, the optimized E-field distribution in the SJBJ-IGBT shows 13.2% improvement of BV. Researching results can provide important reference for reducing the ESW of IGBT.

Optimized 750V SiC MOSFETs for Electric Vehicle Inverter Operation

We report an AEC-Q101-qualified 750V, 15 mΩ planar SiC MOSFETs with a long short circuit withstand time (SCWT) of > 9μs at VDS=400V and VGS=15V and a low specific on-resistance (RON,SP) of 2.1 mΩ.cm2 at VGS=15V designed for xEV traction inverter applications. The RDS(on) at VGS=15V increases from 15mΩ at 25 °C to 21 mΩ at 175 °C. A low turn-on (EON) and turn-off (EOFF) switching energy loss of 95.5μJ and 67μJ at IDS=75A, VDS=400V was measured at 25 °C. The gate oxide lifetime at worst case operating fields of 5MV/cm is >> 20 years.

A Comparative Evaluation of Wide-Bandgap Semiconductors for High-Performance Domestic Induction Heating

This paper presents a comparative evaluation of wide-bandgap power semiconductor devices for domestic induction heating application, which is currently a serious alternative to traditional heating techniques. In the induction heating system, the power transferred to the output depends on the equivalent resistance of the load, and the resistance depends on the operating frequency. Due to the switching characteristics of wide-bandgap power semiconductor devices, an induction heating system can be operated at higher operating frequencies. In this study, SiC and Si semiconductor devices are used in the comparison. These devices are compared according to different evaluation issues such as the turn-off energy losses, turn-off times, current fall time, the power losses of the internal diodes, and the conduction voltage drops issues. To perform the proposed evaluation, the series-resonant half-bridge inverter, which is frequently used in state-of-the-art induction heating systems, has been selected. The device suitability in an induction heating system is analyzed with the help of a test circuit. A comparison is made in terms of criteria determined by using the selected switches in the experimental circuit, which is operated in the 200 W to 1800 W power range and 45 kHz to 125 kHz switching frequency range. System efficiency is measured as 97.3% when Si IGBT is used. In the case of using SiC cascode JFET, the efficiency of the system is increased up to 99%.

Cell Design Consideration in SiC Planar IGBT and Proposal of New SiC IGBT With Improved Performance Trade-Off

In silicon carbide (SiC) planar insulated-gate bipolar transistor (IGBT), a large distance between neighboring p-bodies is beneficial to enhance the on-state conductivity modulation, but will expose the gate oxide to high electric field in off-state. With p-bodies placed closer, the gate oxide field is reduced, but the conductivity modulation is suppressed. In this work, a new SiC planar IGBT with oxide shield is proposed and studied by TCAD simulations. The proposed SiC IGBT achieves improved trade-off between on-state voltage drop (VON) and maximum gate oxide electric field (Eox-m). When a quite larger distance between neighboring p-bodies is adopted in the proposed SiC IGBT, a low VON is obtained, while the Eox-m can be kept at a small value with the oxide shielding structures protecting the gate oxide. Switching characteristics are also studied, and the proposed SiC-IGBT delivers much better trade-off between turn-off energy loss (EOFF) and VON than the conventional SiC planar IGBT.

A low-loss variable-doped trench-insulated gate bipolar transistor with reduced on-state voltage

The performance of a superjunction trench-insulated gate bipolar transistor with variable vertical doping in the epitaxial region along with variation in the collector layer is investigated. The concept of vertical variation transfers the avalanche multiplication point from the epitaxial edges to the middle of the pillar. The proposed device offers increased effective doping in the drift region, which reduces the on-state voltage () without any degradation in the breakdown voltage. Furthermore, the horizontal doping variation in the collector layer supports the phenomenon in two ways: the left section of the collector layer reduces whereas the right portion enables an efficient discharging path, which allows improved switching performance. In addition to this, a reduction in the gate to collector charge () is observed because of the presence of a lightly doped n-region below the gate terminal. A two-dimensional numerical simulation revealed that the proposed device offers a 15.30% reduction in compared with the conventional device. The structural modification offers a 40% reduction in turn-off time, resulting in a reduction in turn-off energy loss ().

Channel current analysis of GaN HEMTs with source sense pin in DC/DC boost converters

The breakdown strength and electron mobility of gallium nitride (GaN) are almost ten and three times higher than those of the silicon devices. Wide band-gap devices have a higher thermal conductivity, higher switching frequency capability, lower on-state resistance and lower power dissipation. Detailed analytical models in the electrical network and channel current variations of these devices during switching intervals are still under investigation. The energy loss and heat dissipation on a power converter can be precisely estimated if the operational modes and the corresponding mathematical models of the device are accurately obtained. Depending on the instantaneous values of the channel current and voltage drops on the components computed from the model, the power dissipation and thermal response can be examined. Prediction of the switching losses of a GaN high electron mobility transistor (HEMT) with a source sense pin can be performed using the instantaneous variation of channel current. In this paper, a detailed analytical model including the stray inductances and parasitic capacitors is derived to obtain the channel current of GaN HEMTs with a source sense pin. The turn-on and turn-off transient energy losses during the switching of a single GaN HEMT device can be computed from the analytical model proposed in this paper using the channel current and drain-source voltage. Results of the derived analytical model, SPICE simulations and experimental work on the DC/DC boost converter are compared.

Characteristics investigation on 4.5kV IGBT with partially narrow mesa and split-gate

Low on-state voltage and low turn-off loss are key issues for IGBT used in HVDC and FACTS. Partial narrow mesa was introduced to improve emitter side contact resistance of IGBT based on Nakagawa limit assumption. However, turn-off loss increases and short circuit sustainability get worse. Split gate separates gate electrode from drift region and reduces gate-collector capacitance to lower turn-off energy loss. Combination partial narrow mesa with split gate can get better gate performance and turn-off characteristics in 4.5kV IGBT. Simulated results with TCAD show proposed models improves switching loss and gate reliability. By adjusting split gap electric filed, split gate shape has an important effect on turn-on characteristics.

A New SiC Planar-Gate IGBT for Injection Enhancement Effect and Low Oxide Field

A new silicon carbide (SiC) planar-gate insulated-gate bipolar transistor (IGBT) is proposed and comprehensively investigated in this paper. Compared to the traditional SiC planar-gate IGBT, the new IGBT boasts a much stronger injection enhancement effect, which leads to a low on-state voltage (VON) approaching the SiC trench-gate IGBT. The strong injection enhancement effect is obtained by a heavily doped carrier storage layer (CSL), which creates a hole barrier under the p-body to hinder minority carriers from being extracted away through the p-body. A p-shield is located at the bottom of the CSL and coupled to the p-body of the IGBT by an embedded p-MOSFET (metal-oxide-semiconductor field effect transistors). In off-state, the heavily doped CSL is shielded by the p-MOSFET clamped p-shield. Thus, a high breakdown voltage is maintained. At the same time, owing to the planar-gate structure, the proposed IGBT does not suffer the high oxide field that threatens the long-term reliability of the trench-gate IGBT. The turn-off characteristics of the new IGBT are also studied, and the turn-off energy loss (EOFF) is similar to the conventional planar-gate IGBT. Therefore, the new IGBT achieves the benefits of both the conventional planar-gate IGBT and the trench-gate IGBT, i.e., a superior VON-EOFF trade-off and a low oxide field.

1.4 kV superjunction IGBT with variation doping profile for enhanced performance parameters

In this paper, stepped doping profile in alternate pillars of Superjunction IGBT structure has been presented. The proposed device structure follows variation doping profile in N and P pillars. The beginning point of avalanche breakdown moves from edges to center of the epitaxial region. Due to this structural modification, we have revealed that the area specific ON resistance of proposed device is reduced by 8% without affecting breakdown voltage (BV). The simulation results show that 15% and 6% reduction in turn-off energy loss (Eoff) and on-state voltage (Von) is achieved. In the proposed device we have improved the trade of factor between ON resistance - breakdown voltage and Eoff -Von. Further temperature analysis is also carried out and it is observed that the proposed device shows no degradation even at higher operating temperature.

Snapback‐free and low‐loss SAG‐LIGBT with self‐driving auxiliary gate

A novel snapback-free and low-loss shorted-anode lateral insulated bipolar transistor (SA-LIGBT) based on silicon on insulator with self-driving auxiliary gate (SAG) in the anode is proposed, named as SAG-LIGBT. The SAG is characterised by metal oxide semiconductor (MOS) structure in the anode, and the gate of the MOS is shorted with the anode electrode, thus self-driving without extra gate signal is achieved. At anode voltage V A = 0, the P-base serving as a barrier to hinder electrons flowing into the N + anode. At V A = V on of the forward conduction, the P-base is depleted to intrinsic, and the anode resistance R SA is increased from R P-base to R intrinsic. At V A = V bus of the turn-off state, the P-base is fully depleted and an electron accumulation layer is formed under the SiO2, thus the R SA is decreased from R intrinsic to R n-channel to provide a low-resistance path for electron current. Consequently, the device not only eliminates the snapback effect but also reduces the turn-off energy loss E off. Therefore, a better trade-off is obtained between V on and E off. At the same V on, the E off of SAG-LIGBT is decreased by 57 and 66% compared with separated shorted-anode LIGBT (SSA-LIGBT) and SA-LIGBT, respectively. Moreover, the SAG-LIGBT exhibits the shorter T off of 80 ns than the SSA-LIGBT and vertical P-collector and N-buffer LIGBT at J A = 100 A/cm2.

An insulated gate bipolar transistor with three-layer poly gate for improved figure of merit

In this study, an insulated gate bipolar transistor (IGBT) with three-layer poly gate is proposed and investigated by TCAD simulation. Here, gate is spilt in two different workfunction materials of N+ poly ( $$\phi _{g}$$ = 4.17 eV) and P+ poly ( $$\phi _{g}$$ = 5.25 eV). Lower workfunction poly layer is sandwiched between higher workfunction poly, connected via a single metal. The gate oxide thickness is varied in x-direction. This leads to improvement in transconductance and reduction in miller capacitance. Thin oxide near the emitter serves good control over the charge carriers in the channel. This deployment of dual material gate in proposed device results in 36% reduction in area-specific on-resistance without any degradation in breakdown voltage. In addition to this, proposed device exhibits improved transient characteristics with 18.5% and 60% reduction in turn-off time and delay, respectively, as compared to conventional device. Further, the turn-off energy loss is reduced by 23.5% and 29.09% reduction in on-state voltage drop is achieved. Furthermore, proposed device offers 23%, 58%, and 30% improvement in FOM1, Baliga figure of merit (BFOM), and FOM2, respectively.

Lateral Variation-Doped Insulated Gate Bipolar Transistor for Low On-State Voltage With Low Loss

In this letter, a new structure of Insulated Gate Bipolar Transistor (IGBT) with lateral variation doping concept in epitaxial region is presented. In the drift region, the lateral variation doping profile acts as a parasitic wide base $\textit {pnp}$ transistor over $\textit {pn}$ superjunction (SJ). This parasitic $\textit {pnp}$ transistor forms Darlington pair with IGBT’s internal $\textit {pnp}$ transistor. The parasitic Darlington pair increases the output current gain and reduces the On-state voltage drop ( ${V}_{\textit {on}}$ ). Apart from this, ${p}^{-}$ -col in the collector layer provides increment in recombination rate of minority charges. An increase in the recombination rate reduces the minority carrier life-time, which further reduces the turn-off and delay time. Improvement in the turn-off time leads to optimize the trade-off between turn-off energy loss ( ${E}_{\textit {off}}$ ) and ${V}_{\textit {on}}$ , as compared to the conventional structure.

Low Turn-Off Loss 4H-SiC Insulated Gate Bipolar Transistor With a Trench Heterojunction Collector

In this work, an improved 4H-SiC insulated gate bipolar transistor (IGBT), or CTH-IGBT, with a trench p-polySi/p-SiC heterojunction on the backside of the device is proposed to reduce the turn-off energy loss ( $E_{off}$ ) and turn-off time ( $T_{off}$ ). The electrical properties of the proposed and contrast structures are all simulated using the ATLAS simulation software to research the working mechanism of this improved structure. For the static performance, the specific ON-resistance ( $R_{on,sp}$ ) and the figure of merit ( ${\mathrm{ FOM}} = V_{BR}^{2}/ R_{on,sp}$ ) are not influenced much as compared to the traditional structure at the same breakdown voltage ( $V_{BR}$ ) of 12 kV. However, with a prominent electron current path formed by the heterojunction region of CTH-IGBT, a very available conduction path to discharge the electrons during turn-off process is proved in this article. The simulation results demonstrate that compared with the traditional structure, the turn-off energy loss of the CTH-IGBT is reduced by 76.4%, while the turn-off time is reduced by 85.0%.

Application of an Efficient Rogowski Coil Sensor for Online Estimation of Turn-Off Energy Loss of Power Diodes

This paper deals with a new application for a special sort of Rogowski coil (RC) sensor in real-time estimation of diode turn-OFF energy loss. The turn-OFF energy loss of power diode is a key metric in designing power electronics circuits. The estimation accuracy of the diode turn-OFF energy loss significantly depends on the accurate extraction of diode reverse-recovery parameters during the turn-OFF process. By far, many methods have been proposed for offline estimation of diode reverse-recovery parameters. However, online estimation of these parameters can also provide worthwhile information for real-time monitoring of power diode and operating power electronics circuit. Specifically, the online estimated energy loss includes information which can be interpreted to obtain general ideas about the diode junction temperature, health status of snubber circuits, and so on. In this paper, a novel approach for online estimation of turn-OFF energy loss of power diodes using an efficient double-layer printed circuit board RC (DLPCBRC) sensor is proposed. The sensor is designed and utilized to acquire the key reverse-recovery parameters of the diode. Based on the extracted reverse-recovery parameters, a sufficiently good estimation of diode turn-OFF energy loss is obtained in real-time. The simulation and experimental results on a typical diode in a boost DC–DC converter are presented to demonstrate the effectiveness of the proposed approach.

Simulation Study of a Low ON-State Voltage Superjunction IGBT With Self-Biased PMOS

In this brief, a novel superjunction (SJ)-insulated-gate bipolar transistor (SJ-IGBT) is proposed and investigated by simulation, where a floating N-base region on the P-pillar region is introduced to form a self-biased PMOS. In the on-state, the PMOS can increase the hole quasi-Fermi potential of the P-pillar region, enhancing the carrier-storage effect in the N-pillar and P-pillar regions and reducing the on-state voltage consequently. In the turn-off transient, because the PMOS can be automatically turned on as a consequence of the potential rise of the P-pillar region with hole accumulation, the proposed SJ-IGBT can be rapidly turned off. The results from TCAD simulation reveal that the on-state voltage of the proposed SJ-IGBT is 46.7% lower than that of the conventional SJ-IGBT with P-pillar shorted with cathode (SJ-IGBT-A) and nearly equivalent to that of the conventional SJ-IGBT with gate on the P-pillar (SJ-IGBT-B). In addition, the off-state breakdown voltage of the proposed SJ-IGBT can roughly keep an identical value with that of SJ-IGBT-A and is 25% higher than that of SJ-IGBT-B. In addition, with the same VON of 1.16 V, the turn-off energy loss of the proposed device is 1.2 mJ/cm2, which is 94.7% lower than that of SJ-IGBT-A and 20% lower than that of SJ-IGBT-B.

Simulation Study of a Low ON-State Voltage and Saturation Current TCIGBT With Diodes

In this brief, a novel trench clustered insulated gate bipolar transistor (TCIGBT) is proposed and investigated by the simulation. In comparison with the conventional TCIGBT, the p-well region is connected to the cathode through two integrated series diodes and a field stop structure is utilized. In the blocking state, the anode voltage is sustained by the p-well/n-drift junction, which makes the breakdown voltage (BV) independent on the dose of n-layer region, eliminating the contradictionbetween theBV and ON-state voltage appearing in the conventional trench insulated gate bipolar transistor (TIGBT). Accordingly, the ON-state voltage can be reduced by increasing the dose of n-layer region. In the ON-state, the electron quasi-Fermi potential of intrinsic drain is clamped at approximately 0.7 V, so that the saturation current is effectively decreased. The results from TCAD simulation indicate that under the same level of BV of the conventional TIGBT the ON-state voltage and saturation current of the proposed device are decreased by 33.6% and 66.6%, respectively. Moreover, a better tradeoff between the turnoff energy loss and ON-state voltage is achieved, i.e., with the same ON-state voltage of 1.29 V, the proposed device shows an improvement of 51.9% in turn-off energy loss.

A Snapback-Free and Low-Loss Shorted-Anode SOI LIGBT With Self-Adaptive Resistance

A novel 600-V snapback-free and low-loss shorted-anode (SA) silicon on insulator lateral insulated gate bipolar transistor (LIGBT) with self-adaptive resistance (SAR) in anode is proposed and investigated by simulation, named SAR LIGBT. The device is characterized by dual anode trenches which are filled with p-type polysilicon and surrounded by oxide, and the dual trenches are shorted with the anode electrode, separated by the low-doped N− region and N+ anode region. At low anode voltage ( $V_{A}$ ), the N− region is fully depleted by p-type polysilicon, serving as a large resistance to hinder electrons flowing into the N+ anode; at high VA, an electron accumulation layer is formed along the anode trenches to provide a low-resistance path for electron current. Consequently, N− region makes the distributed resistances at the anode side ( ${R}_{\text {SA}}$ ) act as a SAR. It not only eliminates the snapback effect but also reduces on-state voltage drop ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) and turn-off energy loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ). Therefore, SAR LIGBT achieves a better tradeoff between $V_{ \mathrm{\scriptscriptstyle ON}}$ and ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ . At the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ , the SAR LIGBT reduces the ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ by 20.6%, 28.1%, and 30.5% compared with those of multisegment anode, segmented trenches in the anode, and SA-NPN LIGBTs, respectively. Moreover, the SAR LIGBT exhibits the lowest ${V}_{ \mathrm{\scriptscriptstyle ON}}$ of 1.71 V and the shortest switching time of 93 ns at $J_{A} = {100}$ A/cm2. In addition, the SAR LIGBT achieves snapback-free with smaller cell pitch than that of separated SA LIGBT.

Novel Low Turn-Off Loss Trench-Gate FS-IGBT With a Hybrid $p^{{+}}/{n}$ Collector Structure

A trench-gate field stop insulated gate bipolar transistor (TFS-IGBT) with a novel hybrid ${p} ^{+}/{n}$ collector structure is proposed to enhance the trade-off relationship between the on-state voltage drop ( ${V} _{\mathrm{ on}}$ ) and the turn-off energy loss ( ${E} _{\mathrm{ off}}$ ). The proposed hybrid collector structure consists of a ${p} ^{+}/{n}$ layer between the ${p} ^{+}$ collector and the field stop layer. During turn-on, the ${p} ^{+}$ regions in the hybrid ${p} ^{+}/{n}$ layer provide high carrier injection efficiency. During turn-off transient, the ${n}$ -regions in the hybrid ${p} ^{+}/{n}$ collector provide fast carrier extraction paths for holes. 2-D numerical simulations comparing a conventional TFS-IGBT, an injection efficiency controlled IGBT with the proposed hybrid ${p} ^{+}/{n}$ collector TFS-IGBT (HC-IGBT) having similar device structures show that for a 1.2 kV rating and with ${V} _{\mathrm{ on}}$ at 1.5 V, the HC-IGBT has an advantage in ${E} _{\mathrm{ off}}$ reduction by 69% and 22%, respectively. Finally, backside mask alignment is not needed for fabricating the proposed hybrid ${p} ^{+}/{n}$ collector structure.